subdev/mmu/vmmgf100.c

0001 /*
0002  * Copyright 2017 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #include "vmm.h"
0023
0024 #include <subdev/fb.h>
0025 #include <subdev/ltc.h>
0026 #include <subdev/timer.h>
0027
0028 #include <nvif/if900d.h>
0029 #include <nvif/unpack.h>
0030
0031 static inline void
0032 gf100_vmm_pgt_pte(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0033           u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
0034 {
0035     u64 base = (addr >> 8) | map->type;
0036     u64 data = base;
0037
0038     if (map->ctag && !(map->next & (1ULL << 44))) {
0039         while (ptes--) {
0040             data = base | ((map->ctag >> 1) << 44);
0041             if (!(map->ctag++ & 1))
0042                 data |= BIT_ULL(60);
0043
0044             VMM_WO064(pt, vmm, ptei++ * 8, data);
0045             base += map->next;
0046         }
0047     } else {
0048         map->type += ptes * map->ctag;
0049
0050         while (ptes--) {
0051             VMM_WO064(pt, vmm, ptei++ * 8, data);
0052             data += map->next;
0053         }
0054     }
0055 }
0056
0057 void
0058 gf100_vmm_pgt_sgl(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0059           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0060 {
0061     VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, gf100_vmm_pgt_pte);
0062 }
0063
0064 void
0065 gf100_vmm_pgt_dma(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0066           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0067 {
0068     if (map->page->shift == PAGE_SHIFT) {
0069         VMM_SPAM(vmm, "DMAA %08x %08x PTE(s)", ptei, ptes);
0070         nvkm_kmap(pt->memory);
0071         while (ptes--) {
0072             const u64 data = (*map->dma++ >> 8) | map->type;
0073             VMM_WO064(pt, vmm, ptei++ * 8, data);
0074             map->type += map->ctag;
0075         }
0076         nvkm_done(pt->memory);
0077         return;
0078     }
0079
0080     VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, gf100_vmm_pgt_pte);
0081 }
0082
0083 void
0084 gf100_vmm_pgt_mem(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0085           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0086 {
0087     VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, gf100_vmm_pgt_pte);
0088 }
0089
0090 void
0091 gf100_vmm_pgt_unmap(struct nvkm_vmm *vmm,
0092             struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0093 {
0094     VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
0095 }
0096
0097 const struct nvkm_vmm_desc_func
0098 gf100_vmm_pgt = {
0099     .unmap = gf100_vmm_pgt_unmap,
0100     .mem = gf100_vmm_pgt_mem,
0101     .dma = gf100_vmm_pgt_dma,
0102     .sgl = gf100_vmm_pgt_sgl,
0103 };
0104
0105 void
0106 gf100_vmm_pgd_pde(struct nvkm_vmm *vmm, struct nvkm_vmm_pt *pgd, u32 pdei)
0107 {
0108     struct nvkm_vmm_pt *pgt = pgd->pde[pdei];
0109     struct nvkm_mmu_pt *pd = pgd->pt[0];
0110     struct nvkm_mmu_pt *pt;
0111     u64 data = 0;
0112
0113     if ((pt = pgt->pt[0])) {
0114         switch (nvkm_memory_target(pt->memory)) {
0115         case NVKM_MEM_TARGET_VRAM: data |= 1ULL << 0; break;
0116         case NVKM_MEM_TARGET_HOST: data |= 2ULL << 0;
0117             data |= BIT_ULL(35); /* VOL */
0118             break;
0119         case NVKM_MEM_TARGET_NCOH: data |= 3ULL << 0; break;
0120         default:
0121             WARN_ON(1);
0122             return;
0123         }
0124         data |= pt->addr >> 8;
0125     }
0126
0127     if ((pt = pgt->pt[1])) {
0128         switch (nvkm_memory_target(pt->memory)) {
0129         case NVKM_MEM_TARGET_VRAM: data |= 1ULL << 32; break;
0130         case NVKM_MEM_TARGET_HOST: data |= 2ULL << 32;
0131             data |= BIT_ULL(34); /* VOL */
0132             break;
0133         case NVKM_MEM_TARGET_NCOH: data |= 3ULL << 32; break;
0134         default:
0135             WARN_ON(1);
0136             return;
0137         }
0138         data |= pt->addr << 24;
0139     }
0140
0141     nvkm_kmap(pd->memory);
0142     VMM_WO064(pd, vmm, pdei * 8, data);
0143     nvkm_done(pd->memory);
0144 }
0145
0146 const struct nvkm_vmm_desc_func
0147 gf100_vmm_pgd = {
0148     .unmap = gf100_vmm_pgt_unmap,
0149     .pde = gf100_vmm_pgd_pde,
0150 };
0151
0152 static const struct nvkm_vmm_desc
0153 gf100_vmm_desc_17_12[] = {
0154     { SPT, 15, 8, 0x1000, &gf100_vmm_pgt },
0155     { PGD, 13, 8, 0x1000, &gf100_vmm_pgd },
0156     {}
0157 };
0158
0159 static const struct nvkm_vmm_desc
0160 gf100_vmm_desc_17_17[] = {
0161     { LPT, 10, 8, 0x1000, &gf100_vmm_pgt },
0162     { PGD, 13, 8, 0x1000, &gf100_vmm_pgd },
0163     {}
0164 };
0165
0166 static const struct nvkm_vmm_desc
0167 gf100_vmm_desc_16_12[] = {
0168     { SPT, 14, 8, 0x1000, &gf100_vmm_pgt },
0169     { PGD, 14, 8, 0x1000, &gf100_vmm_pgd },
0170     {}
0171 };
0172
0173 static const struct nvkm_vmm_desc
0174 gf100_vmm_desc_16_16[] = {
0175     { LPT, 10, 8, 0x1000, &gf100_vmm_pgt },
0176     { PGD, 14, 8, 0x1000, &gf100_vmm_pgd },
0177     {}
0178 };
0179
0180 void
0181 gf100_vmm_invalidate_pdb(struct nvkm_vmm *vmm, u64 addr)
0182 {
0183     struct nvkm_device *device = vmm->mmu->subdev.device;
0184     nvkm_wr32(device, 0x100cb8, addr);
0185 }
0186
0187 void
0188 gf100_vmm_invalidate(struct nvkm_vmm *vmm, u32 type)
0189 {
0190     struct nvkm_device *device = vmm->mmu->subdev.device;
0191     struct nvkm_mmu_pt *pd = vmm->pd->pt[0];
0192     u64 addr = 0;
0193
0194     mutex_lock(&vmm->mmu->mutex);
0195     /* Looks like maybe a "free flush slots" counter, the
0196      * faster you write to 0x100cbc to more it decreases.
0197      */
0198     nvkm_msec(device, 2000,
0199         if (nvkm_rd32(device, 0x100c80) & 0x00ff0000)
0200             break;
0201     );
0202
0203     if (!(type & 0x00000002) /* ALL_PDB. */) {
0204         switch (nvkm_memory_target(pd->memory)) {
0205         case NVKM_MEM_TARGET_VRAM: addr |= 0x00000000; break;
0206         case NVKM_MEM_TARGET_HOST: addr |= 0x00000002; break;
0207         case NVKM_MEM_TARGET_NCOH: addr |= 0x00000003; break;
0208         default:
0209             WARN_ON(1);
0210             break;
0211         }
0212         addr |= (vmm->pd->pt[0]->addr >> 12) << 4;
0213
0214         vmm->func->invalidate_pdb(vmm, addr);
0215     }
0216
0217     nvkm_wr32(device, 0x100cbc, 0x80000000 | type);
0218
0219     /* Wait for flush to be queued? */
0220     nvkm_msec(device, 2000,
0221         if (nvkm_rd32(device, 0x100c80) & 0x00008000)
0222             break;
0223     );
0224     mutex_unlock(&vmm->mmu->mutex);
0225 }
0226
0227 void
0228 gf100_vmm_flush(struct nvkm_vmm *vmm, int depth)
0229 {
0230     u32 type = 0x00000001; /* PAGE_ALL */
0231     if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR]))
0232         type |= 0x00000004; /* HUB_ONLY */
0233     gf100_vmm_invalidate(vmm, type);
0234 }
0235
0236 int
0237 gf100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
0238         struct nvkm_vmm_map *map)
0239 {
0240     const enum nvkm_memory_target target = nvkm_memory_target(map->memory);
0241     const struct nvkm_vmm_page *page = map->page;
0242     const bool gm20x = page->desc->func->sparse != NULL;
0243     union {
0244         struct gf100_vmm_map_vn vn;
0245         struct gf100_vmm_map_v0 v0;
0246     } *args = argv;
0247     struct nvkm_device *device = vmm->mmu->subdev.device;
0248     struct nvkm_memory *memory = map->memory;
0249     u8  kind, kind_inv, priv, ro, vol;
0250     int kindn, aper, ret = -ENOSYS;
0251     const u8 *kindm;
0252
0253     map->next = (1 << page->shift) >> 8;
0254     map->type = map->ctag = 0;
0255
0256     if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
0257         vol  = !!args->v0.vol;
0258         ro   = !!args->v0.ro;
0259         priv = !!args->v0.priv;
0260         kind =   args->v0.kind;
0261     } else
0262     if (!(ret = nvif_unvers(ret, &argv, &argc, args->vn))) {
0263         vol  = target == NVKM_MEM_TARGET_HOST;
0264         ro   = 0;
0265         priv = 0;
0266         kind = 0x00;
0267     } else {
0268         VMM_DEBUG(vmm, "args");
0269         return ret;
0270     }
0271
0272     aper = vmm->func->aper(target);
0273     if (WARN_ON(aper < 0))
0274         return aper;
0275
0276     kindm = vmm->mmu->func->kind(vmm->mmu, &kindn, &kind_inv);
0277     if (kind >= kindn || kindm[kind] == kind_inv) {
0278         VMM_DEBUG(vmm, "kind %02x", kind);
0279         return -EINVAL;
0280     }
0281
0282     if (kindm[kind] != kind) {
0283         u32 comp = (page->shift == 16 && !gm20x) ? 16 : 17;
0284         u32 tags = ALIGN(nvkm_memory_size(memory), 1 << 17) >> comp;
0285         if (aper != 0 || !(page->type & NVKM_VMM_PAGE_COMP)) {
0286             VMM_DEBUG(vmm, "comp %d %02x", aper, page->type);
0287             return -EINVAL;
0288         }
0289
0290         ret = nvkm_memory_tags_get(memory, device, tags,
0291                        nvkm_ltc_tags_clear,
0292                        &map->tags);
0293         if (ret) {
0294             VMM_DEBUG(vmm, "comp %d", ret);
0295             return ret;
0296         }
0297
0298         if (map->tags->mn) {
0299             u64 tags = map->tags->mn->offset + (map->offset >> 17);
0300             if (page->shift == 17 || !gm20x) {
0301                 map->type |= tags << 44;
0302                 map->ctag |= 1ULL << 44;
0303                 map->next |= 1ULL << 44;
0304             } else {
0305                 map->ctag |= tags << 1 | 1;
0306             }
0307         } else {
0308             kind = kindm[kind];
0309         }
0310     }
0311
0312     map->type |= BIT(0);
0313     map->type |= (u64)priv << 1;
0314     map->type |= (u64)  ro << 2;
0315     map->type |= (u64) vol << 32;
0316     map->type |= (u64)aper << 33;
0317     map->type |= (u64)kind << 36;
0318     return 0;
0319 }
0320
0321 int
0322 gf100_vmm_aper(enum nvkm_memory_target target)
0323 {
0324     switch (target) {
0325     case NVKM_MEM_TARGET_VRAM: return 0;
0326     case NVKM_MEM_TARGET_HOST: return 2;
0327     case NVKM_MEM_TARGET_NCOH: return 3;
0328     default:
0329         return -EINVAL;
0330     }
0331 }
0332
0333 void
0334 gf100_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
0335 {
0336     nvkm_fo64(inst, 0x0200, 0x00000000, 2);
0337 }
0338
0339 int
0340 gf100_vmm_join_(struct nvkm_vmm *vmm, struct nvkm_memory *inst, u64 base)
0341 {
0342     struct nvkm_mmu_pt *pd = vmm->pd->pt[0];
0343
0344     switch (nvkm_memory_target(pd->memory)) {
0345     case NVKM_MEM_TARGET_VRAM: base |= 0ULL << 0; break;
0346     case NVKM_MEM_TARGET_HOST: base |= 2ULL << 0;
0347         base |= BIT_ULL(2) /* VOL. */;
0348         break;
0349     case NVKM_MEM_TARGET_NCOH: base |= 3ULL << 0; break;
0350     default:
0351         WARN_ON(1);
0352         return -EINVAL;
0353     }
0354     base |= pd->addr;
0355
0356     nvkm_kmap(inst);
0357     nvkm_wo64(inst, 0x0200, base);
0358     nvkm_wo64(inst, 0x0208, vmm->limit - 1);
0359     nvkm_done(inst);
0360     return 0;
0361 }
0362
0363 int
0364 gf100_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
0365 {
0366     return gf100_vmm_join_(vmm, inst, 0);
0367 }
0368
0369 static const struct nvkm_vmm_func
0370 gf100_vmm_17 = {
0371     .join = gf100_vmm_join,
0372     .part = gf100_vmm_part,
0373     .aper = gf100_vmm_aper,
0374     .valid = gf100_vmm_valid,
0375     .flush = gf100_vmm_flush,
0376     .invalidate_pdb = gf100_vmm_invalidate_pdb,
0377     .page = {
0378         { 17, &gf100_vmm_desc_17_17[0], NVKM_VMM_PAGE_xVxC },
0379         { 12, &gf100_vmm_desc_17_12[0], NVKM_VMM_PAGE_xVHx },
0380         {}
0381     }
0382 };
0383
0384 static const struct nvkm_vmm_func
0385 gf100_vmm_16 = {
0386     .join = gf100_vmm_join,
0387     .part = gf100_vmm_part,
0388     .aper = gf100_vmm_aper,
0389     .valid = gf100_vmm_valid,
0390     .flush = gf100_vmm_flush,
0391     .invalidate_pdb = gf100_vmm_invalidate_pdb,
0392     .page = {
0393         { 16, &gf100_vmm_desc_16_16[0], NVKM_VMM_PAGE_xVxC },
0394         { 12, &gf100_vmm_desc_16_12[0], NVKM_VMM_PAGE_xVHx },
0395         {}
0396     }
0397 };
0398
0399 int
0400 gf100_vmm_new_(const struct nvkm_vmm_func *func_16,
0401            const struct nvkm_vmm_func *func_17,
0402            struct nvkm_mmu *mmu, bool managed, u64 addr, u64 size,
0403            void *argv, u32 argc, struct lock_class_key *key,
0404            const char *name, struct nvkm_vmm **pvmm)
0405 {
0406     switch (mmu->subdev.device->fb->page) {
0407     case 16: return nv04_vmm_new_(func_16, mmu, 0, managed, addr, size,
0408                       argv, argc, key, name, pvmm);
0409     case 17: return nv04_vmm_new_(func_17, mmu, 0, managed, addr, size,
0410                       argv, argc, key, name, pvmm);
0411     default:
0412         WARN_ON(1);
0413         return -EINVAL;
0414     }
0415 }
0416
0417 int
0418 gf100_vmm_new(struct nvkm_mmu *mmu, bool managed, u64 addr, u64 size,
0419           void *argv, u32 argc, struct lock_class_key *key,
0420           const char *name, struct nvkm_vmm **pvmm)
0421 {
0422     return gf100_vmm_new_(&gf100_vmm_16, &gf100_vmm_17, mmu, managed, addr,
0423                   size, argv, argc, key, name, pvmm);
0424 }