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0024 #include "priv.h"
0025
0026 static const struct nvkm_mc_map
0027 gt215_mc_reset[] = {
0028 { 0x04008000, NVKM_ENGINE_MSVLD },
0029 { 0x01020000, NVKM_ENGINE_MSPDEC },
0030 { 0x00802000, NVKM_ENGINE_CE, 0 },
0031 { 0x00400002, NVKM_ENGINE_MSPPP },
0032 { 0x00201000, NVKM_ENGINE_GR },
0033 { 0x00000100, NVKM_ENGINE_FIFO },
0034 {}
0035 };
0036
0037 static const struct nvkm_mc_map
0038 gt215_mc_intr[] = {
0039 { 0x04000000, NVKM_ENGINE_DISP },
0040 { 0x00400000, NVKM_ENGINE_CE, 0 },
0041 { 0x00020000, NVKM_ENGINE_MSPDEC },
0042 { 0x00008000, NVKM_ENGINE_MSVLD },
0043 { 0x00001000, NVKM_ENGINE_GR },
0044 { 0x00000100, NVKM_ENGINE_FIFO },
0045 { 0x00000001, NVKM_ENGINE_MSPPP },
0046 { 0x00429101, NVKM_SUBDEV_FB },
0047 { 0x10000000, NVKM_SUBDEV_BUS },
0048 { 0x00200000, NVKM_SUBDEV_GPIO },
0049 { 0x00200000, NVKM_SUBDEV_I2C },
0050 { 0x00100000, NVKM_SUBDEV_TIMER },
0051 { 0x00080000, NVKM_SUBDEV_THERM },
0052 { 0x00040000, NVKM_SUBDEV_PMU },
0053 {},
0054 };
0055
0056 static void
0057 gt215_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat)
0058 {
0059 nvkm_mask(mc->subdev.device, 0x000640, mask, stat);
0060 }
0061
0062 static const struct nvkm_mc_func
0063 gt215_mc = {
0064 .init = nv50_mc_init,
0065 .intr = gt215_mc_intr,
0066 .intr_unarm = nv04_mc_intr_unarm,
0067 .intr_rearm = nv04_mc_intr_rearm,
0068 .intr_mask = gt215_mc_intr_mask,
0069 .intr_stat = nv04_mc_intr_stat,
0070 .reset = gt215_mc_reset,
0071 };
0072
0073 int
0074 gt215_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
0075 {
0076 return nvkm_mc_new_(>215_mc, device, type, inst, pmc);
0077 }