subdev/mc/gp100.c

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #define gp100_mc(p) container_of((p), struct gp100_mc, base)
0025 #include "priv.h"
0026
0027 struct gp100_mc {
0028     struct nvkm_mc base;
0029     spinlock_t lock;
0030     bool intr;
0031     u32 mask;
0032 };
0033
0034 static void
0035 gp100_mc_intr_update(struct gp100_mc *mc)
0036 {
0037     struct nvkm_device *device = mc->base.subdev.device;
0038     u32 mask = mc->intr ? mc->mask : 0, i;
0039     for (i = 0; i < 2; i++) {
0040         nvkm_wr32(device, 0x000180 + (i * 0x04), ~mask);
0041         nvkm_wr32(device, 0x000160 + (i * 0x04),  mask);
0042     }
0043 }
0044
0045 void
0046 gp100_mc_intr_unarm(struct nvkm_mc *base)
0047 {
0048     struct gp100_mc *mc = gp100_mc(base);
0049     unsigned long flags;
0050     spin_lock_irqsave(&mc->lock, flags);
0051     mc->intr = false;
0052     gp100_mc_intr_update(mc);
0053     spin_unlock_irqrestore(&mc->lock, flags);
0054 }
0055
0056 void
0057 gp100_mc_intr_rearm(struct nvkm_mc *base)
0058 {
0059     struct gp100_mc *mc = gp100_mc(base);
0060     unsigned long flags;
0061     spin_lock_irqsave(&mc->lock, flags);
0062     mc->intr = true;
0063     gp100_mc_intr_update(mc);
0064     spin_unlock_irqrestore(&mc->lock, flags);
0065 }
0066
0067 void
0068 gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr)
0069 {
0070     struct gp100_mc *mc = gp100_mc(base);
0071     unsigned long flags;
0072     spin_lock_irqsave(&mc->lock, flags);
0073     mc->mask = (mc->mask & ~mask) | intr;
0074     gp100_mc_intr_update(mc);
0075     spin_unlock_irqrestore(&mc->lock, flags);
0076 }
0077
0078 const struct nvkm_mc_map
0079 gp100_mc_intr[] = {
0080     { 0x04000000, NVKM_ENGINE_DISP },
0081     { 0x00000100, NVKM_ENGINE_FIFO },
0082     { 0x00000200, NVKM_SUBDEV_FAULT },
0083     { 0x40000000, NVKM_SUBDEV_PRIVRING },
0084     { 0x10000000, NVKM_SUBDEV_BUS },
0085     { 0x08000000, NVKM_SUBDEV_FB },
0086     { 0x02000000, NVKM_SUBDEV_LTC },
0087     { 0x01000000, NVKM_SUBDEV_PMU },
0088     { 0x00200000, NVKM_SUBDEV_GPIO },
0089     { 0x00200000, NVKM_SUBDEV_I2C },
0090     { 0x00100000, NVKM_SUBDEV_TIMER },
0091     { 0x00040000, NVKM_SUBDEV_THERM },
0092     { 0x00002000, NVKM_SUBDEV_FB },
0093     {},
0094 };
0095
0096 static const struct nvkm_mc_func
0097 gp100_mc = {
0098     .init = nv50_mc_init,
0099     .intr = gp100_mc_intr,
0100     .intr_unarm = gp100_mc_intr_unarm,
0101     .intr_rearm = gp100_mc_intr_rearm,
0102     .intr_mask = gp100_mc_intr_mask,
0103     .intr_stat = gf100_mc_intr_stat,
0104     .reset = gk104_mc_reset,
0105 };
0106
0107 int
0108 gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device,
0109           enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
0110 {
0111     struct gp100_mc *mc;
0112
0113     if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL)))
0114         return -ENOMEM;
0115     nvkm_mc_ctor(func, device, type, inst, &mc->base);
0116     *pmc = &mc->base;
0117
0118     spin_lock_init(&mc->lock);
0119     mc->intr = false;
0120     mc->mask = 0x7fffffff;
0121     return 0;
0122 }
0123
0124 int
0125 gp100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
0126 {
0127     return gp100_mc_new_(&gp100_mc, device, type, inst, pmc);
0128 }