subdev/instmem/gk20a.c

0001 /*
0002  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0019  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0020  * DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 /*
0024  * GK20A does not have dedicated video memory, and to accurately represent this
0025  * fact Nouveau will not create a RAM device for it. Therefore its instmem
0026  * implementation must be done directly on top of system memory, while
0027  * preserving coherency for read and write operations.
0028  *
0029  * Instmem can be allocated through two means:
0030  * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory
0031  *    pages contiguous to the GPU. This is the preferred way.
0032  * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically
0033  *    contiguous memory.
0034  *
0035  * In both cases CPU read and writes are performed by creating a write-combined
0036  * mapping. The GPU L2 cache must thus be flushed/invalidated when required. To
0037  * be conservative we do this every time we acquire or release an instobj, but
0038  * ideally L2 management should be handled at a higher level.
0039  *
0040  * To improve performance, CPU mappings are not removed upon instobj release.
0041  * Instead they are placed into a LRU list to be recycled when the mapped space
0042  * goes beyond a certain threshold. At the moment this limit is 1MB.
0043  */
0044 #include "priv.h"
0045
0046 #include <core/memory.h>
0047 #include <core/tegra.h>
0048 #include <subdev/ltc.h>
0049 #include <subdev/mmu.h>
0050
0051 struct gk20a_instobj {
0052     struct nvkm_memory memory;
0053     struct nvkm_mm_node *mn;
0054     struct gk20a_instmem *imem;
0055
0056     /* CPU mapping */
0057     u32 *vaddr;
0058 };
0059 #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory)
0060
0061 /*
0062  * Used for objects allocated using the DMA API
0063  */
0064 struct gk20a_instobj_dma {
0065     struct gk20a_instobj base;
0066
0067     dma_addr_t handle;
0068     struct nvkm_mm_node r;
0069 };
0070 #define gk20a_instobj_dma(p) \
0071     container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base)
0072
0073 /*
0074  * Used for objects flattened using the IOMMU API
0075  */
0076 struct gk20a_instobj_iommu {
0077     struct gk20a_instobj base;
0078
0079     /* to link into gk20a_instmem::vaddr_lru */
0080     struct list_head vaddr_node;
0081     /* how many clients are using vaddr? */
0082     u32 use_cpt;
0083
0084     /* will point to the higher half of pages */
0085     dma_addr_t *dma_addrs;
0086     /* array of base.mem->size pages (+ dma_addr_ts) */
0087     struct page *pages[];
0088 };
0089 #define gk20a_instobj_iommu(p) \
0090     container_of(gk20a_instobj(p), struct gk20a_instobj_iommu, base)
0091
0092 struct gk20a_instmem {
0093     struct nvkm_instmem base;
0094
0095     /* protects vaddr_* and gk20a_instobj::vaddr* */
0096     struct mutex lock;
0097
0098     /* CPU mappings LRU */
0099     unsigned int vaddr_use;
0100     unsigned int vaddr_max;
0101     struct list_head vaddr_lru;
0102
0103     /* Only used if IOMMU if present */
0104     struct mutex *mm_mutex;
0105     struct nvkm_mm *mm;
0106     struct iommu_domain *domain;
0107     unsigned long iommu_pgshift;
0108     u16 iommu_bit;
0109
0110     /* Only used by DMA API */
0111     unsigned long attrs;
0112 };
0113 #define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base)
0114
0115 static enum nvkm_memory_target
0116 gk20a_instobj_target(struct nvkm_memory *memory)
0117 {
0118     return NVKM_MEM_TARGET_NCOH;
0119 }
0120
0121 static u8
0122 gk20a_instobj_page(struct nvkm_memory *memory)
0123 {
0124     return 12;
0125 }
0126
0127 static u64
0128 gk20a_instobj_addr(struct nvkm_memory *memory)
0129 {
0130     return (u64)gk20a_instobj(memory)->mn->offset << 12;
0131 }
0132
0133 static u64
0134 gk20a_instobj_size(struct nvkm_memory *memory)
0135 {
0136     return (u64)gk20a_instobj(memory)->mn->length << 12;
0137 }
0138
0139 /*
0140  * Recycle the vaddr of obj. Must be called with gk20a_instmem::lock held.
0141  */
0142 static void
0143 gk20a_instobj_iommu_recycle_vaddr(struct gk20a_instobj_iommu *obj)
0144 {
0145     struct gk20a_instmem *imem = obj->base.imem;
0146     /* there should not be any user left... */
0147     WARN_ON(obj->use_cpt);
0148     list_del(&obj->vaddr_node);
0149     vunmap(obj->base.vaddr);
0150     obj->base.vaddr = NULL;
0151     imem->vaddr_use -= nvkm_memory_size(&obj->base.memory);
0152     nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use,
0153            imem->vaddr_max);
0154 }
0155
0156 /*
0157  * Must be called while holding gk20a_instmem::lock
0158  */
0159 static void
0160 gk20a_instmem_vaddr_gc(struct gk20a_instmem *imem, const u64 size)
0161 {
0162     while (imem->vaddr_use + size > imem->vaddr_max) {
0163         /* no candidate that can be unmapped, abort... */
0164         if (list_empty(&imem->vaddr_lru))
0165             break;
0166
0167         gk20a_instobj_iommu_recycle_vaddr(
0168                 list_first_entry(&imem->vaddr_lru,
0169                 struct gk20a_instobj_iommu, vaddr_node));
0170     }
0171 }
0172
0173 static void __iomem *
0174 gk20a_instobj_acquire_dma(struct nvkm_memory *memory)
0175 {
0176     struct gk20a_instobj *node = gk20a_instobj(memory);
0177     struct gk20a_instmem *imem = node->imem;
0178     struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
0179
0180     nvkm_ltc_flush(ltc);
0181
0182     return node->vaddr;
0183 }
0184
0185 static void __iomem *
0186 gk20a_instobj_acquire_iommu(struct nvkm_memory *memory)
0187 {
0188     struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
0189     struct gk20a_instmem *imem = node->base.imem;
0190     struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
0191     const u64 size = nvkm_memory_size(memory);
0192
0193     nvkm_ltc_flush(ltc);
0194
0195     mutex_lock(&imem->lock);
0196
0197     if (node->base.vaddr) {
0198         if (!node->use_cpt) {
0199             /* remove from LRU list since mapping in use again */
0200             list_del(&node->vaddr_node);
0201         }
0202         goto out;
0203     }
0204
0205     /* try to free some address space if we reached the limit */
0206     gk20a_instmem_vaddr_gc(imem, size);
0207
0208     /* map the pages */
0209     node->base.vaddr = vmap(node->pages, size >> PAGE_SHIFT, VM_MAP,
0210                 pgprot_writecombine(PAGE_KERNEL));
0211     if (!node->base.vaddr) {
0212         nvkm_error(&imem->base.subdev, "cannot map instobj - "
0213                "this is not going to end well...\n");
0214         goto out;
0215     }
0216
0217     imem->vaddr_use += size;
0218     nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n",
0219            imem->vaddr_use, imem->vaddr_max);
0220
0221 out:
0222     node->use_cpt++;
0223     mutex_unlock(&imem->lock);
0224
0225     return node->base.vaddr;
0226 }
0227
0228 static void
0229 gk20a_instobj_release_dma(struct nvkm_memory *memory)
0230 {
0231     struct gk20a_instobj *node = gk20a_instobj(memory);
0232     struct gk20a_instmem *imem = node->imem;
0233     struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
0234
0235     /* in case we got a write-combined mapping */
0236     wmb();
0237     nvkm_ltc_invalidate(ltc);
0238 }
0239
0240 static void
0241 gk20a_instobj_release_iommu(struct nvkm_memory *memory)
0242 {
0243     struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
0244     struct gk20a_instmem *imem = node->base.imem;
0245     struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
0246
0247     mutex_lock(&imem->lock);
0248
0249     /* we should at least have one user to release... */
0250     if (WARN_ON(node->use_cpt == 0))
0251         goto out;
0252
0253     /* add unused objs to the LRU list to recycle their mapping */
0254     if (--node->use_cpt == 0)
0255         list_add_tail(&node->vaddr_node, &imem->vaddr_lru);
0256
0257 out:
0258     mutex_unlock(&imem->lock);
0259
0260     wmb();
0261     nvkm_ltc_invalidate(ltc);
0262 }
0263
0264 static u32
0265 gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset)
0266 {
0267     struct gk20a_instobj *node = gk20a_instobj(memory);
0268
0269     return node->vaddr[offset / 4];
0270 }
0271
0272 static void
0273 gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data)
0274 {
0275     struct gk20a_instobj *node = gk20a_instobj(memory);
0276
0277     node->vaddr[offset / 4] = data;
0278 }
0279
0280 static int
0281 gk20a_instobj_map(struct nvkm_memory *memory, u64 offset, struct nvkm_vmm *vmm,
0282           struct nvkm_vma *vma, void *argv, u32 argc)
0283 {
0284     struct gk20a_instobj *node = gk20a_instobj(memory);
0285     struct nvkm_vmm_map map = {
0286         .memory = &node->memory,
0287         .offset = offset,
0288         .mem = node->mn,
0289     };
0290
0291     return nvkm_vmm_map(vmm, vma, argv, argc, &map);
0292 }
0293
0294 static void *
0295 gk20a_instobj_dtor_dma(struct nvkm_memory *memory)
0296 {
0297     struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory);
0298     struct gk20a_instmem *imem = node->base.imem;
0299     struct device *dev = imem->base.subdev.device->dev;
0300
0301     if (unlikely(!node->base.vaddr))
0302         goto out;
0303
0304     dma_free_attrs(dev, (u64)node->base.mn->length << PAGE_SHIFT,
0305                node->base.vaddr, node->handle, imem->attrs);
0306
0307 out:
0308     return node;
0309 }
0310
0311 static void *
0312 gk20a_instobj_dtor_iommu(struct nvkm_memory *memory)
0313 {
0314     struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
0315     struct gk20a_instmem *imem = node->base.imem;
0316     struct device *dev = imem->base.subdev.device->dev;
0317     struct nvkm_mm_node *r = node->base.mn;
0318     int i;
0319
0320     if (unlikely(!r))
0321         goto out;
0322
0323     mutex_lock(&imem->lock);
0324
0325     /* vaddr has already been recycled */
0326     if (node->base.vaddr)
0327         gk20a_instobj_iommu_recycle_vaddr(node);
0328
0329     mutex_unlock(&imem->lock);
0330
0331     /* clear IOMMU bit to unmap pages */
0332     r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift);
0333
0334     /* Unmap pages from GPU address space and free them */
0335     for (i = 0; i < node->base.mn->length; i++) {
0336         iommu_unmap(imem->domain,
0337                 (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE);
0338         dma_unmap_page(dev, node->dma_addrs[i], PAGE_SIZE,
0339                    DMA_BIDIRECTIONAL);
0340         __free_page(node->pages[i]);
0341     }
0342
0343     /* Release area from GPU address space */
0344     mutex_lock(imem->mm_mutex);
0345     nvkm_mm_free(imem->mm, &r);
0346     mutex_unlock(imem->mm_mutex);
0347
0348 out:
0349     return node;
0350 }
0351
0352 static const struct nvkm_memory_func
0353 gk20a_instobj_func_dma = {
0354     .dtor = gk20a_instobj_dtor_dma,
0355     .target = gk20a_instobj_target,
0356     .page = gk20a_instobj_page,
0357     .addr = gk20a_instobj_addr,
0358     .size = gk20a_instobj_size,
0359     .acquire = gk20a_instobj_acquire_dma,
0360     .release = gk20a_instobj_release_dma,
0361     .map = gk20a_instobj_map,
0362 };
0363
0364 static const struct nvkm_memory_func
0365 gk20a_instobj_func_iommu = {
0366     .dtor = gk20a_instobj_dtor_iommu,
0367     .target = gk20a_instobj_target,
0368     .page = gk20a_instobj_page,
0369     .addr = gk20a_instobj_addr,
0370     .size = gk20a_instobj_size,
0371     .acquire = gk20a_instobj_acquire_iommu,
0372     .release = gk20a_instobj_release_iommu,
0373     .map = gk20a_instobj_map,
0374 };
0375
0376 static const struct nvkm_memory_ptrs
0377 gk20a_instobj_ptrs = {
0378     .rd32 = gk20a_instobj_rd32,
0379     .wr32 = gk20a_instobj_wr32,
0380 };
0381
0382 static int
0383 gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align,
0384                struct gk20a_instobj **_node)
0385 {
0386     struct gk20a_instobj_dma *node;
0387     struct nvkm_subdev *subdev = &imem->base.subdev;
0388     struct device *dev = subdev->device->dev;
0389
0390     if (!(node = kzalloc(sizeof(*node), GFP_KERNEL)))
0391         return -ENOMEM;
0392     *_node = &node->base;
0393
0394     nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory);
0395     node->base.memory.ptrs = &gk20a_instobj_ptrs;
0396
0397     node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT,
0398                        &node->handle, GFP_KERNEL,
0399                        imem->attrs);
0400     if (!node->base.vaddr) {
0401         nvkm_error(subdev, "cannot allocate DMA memory\n");
0402         return -ENOMEM;
0403     }
0404
0405     /* alignment check */
0406     if (unlikely(node->handle & (align - 1)))
0407         nvkm_warn(subdev,
0408               "memory not aligned as requested: %pad (0x%x)\n",
0409               &node->handle, align);
0410
0411     /* present memory for being mapped using small pages */
0412     node->r.type = 12;
0413     node->r.offset = node->handle >> 12;
0414     node->r.length = (npages << PAGE_SHIFT) >> 12;
0415
0416     node->base.mn = &node->r;
0417     return 0;
0418 }
0419
0420 static int
0421 gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align,
0422              struct gk20a_instobj **_node)
0423 {
0424     struct gk20a_instobj_iommu *node;
0425     struct nvkm_subdev *subdev = &imem->base.subdev;
0426     struct device *dev = subdev->device->dev;
0427     struct nvkm_mm_node *r;
0428     int ret;
0429     int i;
0430
0431     /*
0432      * despite their variable size, instmem allocations are small enough
0433      * (< 1 page) to be handled by kzalloc
0434      */
0435     if (!(node = kzalloc(sizeof(*node) + ((sizeof(node->pages[0]) +
0436                  sizeof(*node->dma_addrs)) * npages), GFP_KERNEL)))
0437         return -ENOMEM;
0438     *_node = &node->base;
0439     node->dma_addrs = (void *)(node->pages + npages);
0440
0441     nvkm_memory_ctor(&gk20a_instobj_func_iommu, &node->base.memory);
0442     node->base.memory.ptrs = &gk20a_instobj_ptrs;
0443
0444     /* Allocate backing memory */
0445     for (i = 0; i < npages; i++) {
0446         struct page *p = alloc_page(GFP_KERNEL);
0447         dma_addr_t dma_adr;
0448
0449         if (p == NULL) {
0450             ret = -ENOMEM;
0451             goto free_pages;
0452         }
0453         node->pages[i] = p;
0454         dma_adr = dma_map_page(dev, p, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
0455         if (dma_mapping_error(dev, dma_adr)) {
0456             nvkm_error(subdev, "DMA mapping error!\n");
0457             ret = -ENOMEM;
0458             goto free_pages;
0459         }
0460         node->dma_addrs[i] = dma_adr;
0461     }
0462
0463     mutex_lock(imem->mm_mutex);
0464     /* Reserve area from GPU address space */
0465     ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages,
0466                align >> imem->iommu_pgshift, &r);
0467     mutex_unlock(imem->mm_mutex);
0468     if (ret) {
0469         nvkm_error(subdev, "IOMMU space is full!\n");
0470         goto free_pages;
0471     }
0472
0473     /* Map into GPU address space */
0474     for (i = 0; i < npages; i++) {
0475         u32 offset = (r->offset + i) << imem->iommu_pgshift;
0476
0477         ret = iommu_map(imem->domain, offset, node->dma_addrs[i],
0478                 PAGE_SIZE, IOMMU_READ | IOMMU_WRITE);
0479         if (ret < 0) {
0480             nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret);
0481
0482             while (i-- > 0) {
0483                 offset -= PAGE_SIZE;
0484                 iommu_unmap(imem->domain, offset, PAGE_SIZE);
0485             }
0486             goto release_area;
0487         }
0488     }
0489
0490     /* IOMMU bit tells that an address is to be resolved through the IOMMU */
0491     r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift);
0492
0493     node->base.mn = r;
0494     return 0;
0495
0496 release_area:
0497     mutex_lock(imem->mm_mutex);
0498     nvkm_mm_free(imem->mm, &r);
0499     mutex_unlock(imem->mm_mutex);
0500
0501 free_pages:
0502     for (i = 0; i < npages && node->pages[i] != NULL; i++) {
0503         dma_addr_t dma_addr = node->dma_addrs[i];
0504         if (dma_addr)
0505             dma_unmap_page(dev, dma_addr, PAGE_SIZE,
0506                        DMA_BIDIRECTIONAL);
0507         __free_page(node->pages[i]);
0508     }
0509
0510     return ret;
0511 }
0512
0513 static int
0514 gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
0515           struct nvkm_memory **pmemory)
0516 {
0517     struct gk20a_instmem *imem = gk20a_instmem(base);
0518     struct nvkm_subdev *subdev = &imem->base.subdev;
0519     struct gk20a_instobj *node = NULL;
0520     int ret;
0521
0522     nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__,
0523            imem->domain ? "IOMMU" : "DMA", size, align);
0524
0525     /* Round size and align to page bounds */
0526     size = max(roundup(size, PAGE_SIZE), PAGE_SIZE);
0527     align = max(roundup(align, PAGE_SIZE), PAGE_SIZE);
0528
0529     if (imem->domain)
0530         ret = gk20a_instobj_ctor_iommu(imem, size >> PAGE_SHIFT,
0531                            align, &node);
0532     else
0533         ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT,
0534                          align, &node);
0535     *pmemory = node ? &node->memory : NULL;
0536     if (ret)
0537         return ret;
0538
0539     node->imem = imem;
0540
0541     nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
0542            size, align, (u64)node->mn->offset << 12);
0543
0544     return 0;
0545 }
0546
0547 static void *
0548 gk20a_instmem_dtor(struct nvkm_instmem *base)
0549 {
0550     struct gk20a_instmem *imem = gk20a_instmem(base);
0551
0552     /* perform some sanity checks... */
0553     if (!list_empty(&imem->vaddr_lru))
0554         nvkm_warn(&base->subdev, "instobj LRU not empty!\n");
0555
0556     if (imem->vaddr_use != 0)
0557         nvkm_warn(&base->subdev, "instobj vmap area not empty! "
0558               "0x%x bytes still mapped\n", imem->vaddr_use);
0559
0560     return imem;
0561 }
0562
0563 static const struct nvkm_instmem_func
0564 gk20a_instmem = {
0565     .dtor = gk20a_instmem_dtor,
0566     .memory_new = gk20a_instobj_new,
0567     .zero = false,
0568 };
0569
0570 int
0571 gk20a_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0572           struct nvkm_instmem **pimem)
0573 {
0574     struct nvkm_device_tegra *tdev = device->func->tegra(device);
0575     struct gk20a_instmem *imem;
0576
0577     if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
0578         return -ENOMEM;
0579     nvkm_instmem_ctor(&gk20a_instmem, device, type, inst, &imem->base);
0580     mutex_init(&imem->lock);
0581     *pimem = &imem->base;
0582
0583     /* do not allow more than 1MB of CPU-mapped instmem */
0584     imem->vaddr_use = 0;
0585     imem->vaddr_max = 0x100000;
0586     INIT_LIST_HEAD(&imem->vaddr_lru);
0587
0588     if (tdev->iommu.domain) {
0589         imem->mm_mutex = &tdev->iommu.mutex;
0590         imem->mm = &tdev->iommu.mm;
0591         imem->domain = tdev->iommu.domain;
0592         imem->iommu_pgshift = tdev->iommu.pgshift;
0593         imem->iommu_bit = tdev->func->iommu_bit;
0594
0595         nvkm_info(&imem->base.subdev, "using IOMMU\n");
0596     } else {
0597         imem->attrs = DMA_ATTR_WEAK_ORDERING |
0598                   DMA_ATTR_WRITE_COMBINE;
0599
0600         nvkm_info(&imem->base.subdev, "using DMA API\n");
0601     }
0602
0603     return 0;
0604 }