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0024 #include "priv.h"
0025
0026 void
0027 nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
0028 {
0029 struct nvkm_device *device = gpio->subdev.device;
0030 struct nvkm_bios *bios = device->bios;
0031 u8 ver, len;
0032 u16 entry;
0033 int ent = -1;
0034
0035 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
0036 static const u32 regs[] = { 0xe100, 0xe28c };
0037 u32 data = nvbios_rd32(bios, entry);
0038 u8 line = (data & 0x0000001f);
0039 u8 func = (data & 0x0000ff00) >> 8;
0040 u8 defs = !!(data & 0x01000000);
0041 u8 unk0 = !!(data & 0x02000000);
0042 u8 unk1 = !!(data & 0x04000000);
0043 u32 val = (unk1 << 16) | unk0;
0044 u32 reg = regs[line >> 4];
0045 u32 lsh = line & 0x0f;
0046
0047 if ( func == DCB_GPIO_UNUSED ||
0048 (match != DCB_GPIO_UNUSED && match != func))
0049 continue;
0050
0051 nvkm_gpio_set(gpio, 0, func, line, defs);
0052
0053 nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh);
0054 }
0055 }
0056
0057 static int
0058 nv50_gpio_location(int line, u32 *reg, u32 *shift)
0059 {
0060 const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
0061
0062 if (line >= 32)
0063 return -EINVAL;
0064
0065 *reg = nv50_gpio_reg[line >> 3];
0066 *shift = (line & 7) << 2;
0067 return 0;
0068 }
0069
0070 int
0071 nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
0072 {
0073 struct nvkm_device *device = gpio->subdev.device;
0074 u32 reg, shift;
0075
0076 if (nv50_gpio_location(line, ®, &shift))
0077 return -EINVAL;
0078
0079 nvkm_mask(device, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift);
0080 return 0;
0081 }
0082
0083 int
0084 nv50_gpio_sense(struct nvkm_gpio *gpio, int line)
0085 {
0086 struct nvkm_device *device = gpio->subdev.device;
0087 u32 reg, shift;
0088
0089 if (nv50_gpio_location(line, ®, &shift))
0090 return -EINVAL;
0091
0092 return !!(nvkm_rd32(device, reg) & (4 << shift));
0093 }
0094
0095 static void
0096 nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
0097 {
0098 struct nvkm_device *device = gpio->subdev.device;
0099 u32 intr = nvkm_rd32(device, 0x00e054);
0100 u32 stat = nvkm_rd32(device, 0x00e050) & intr;
0101 *lo = (stat & 0xffff0000) >> 16;
0102 *hi = (stat & 0x0000ffff);
0103 nvkm_wr32(device, 0x00e054, intr);
0104 }
0105
0106 static void
0107 nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
0108 {
0109 struct nvkm_device *device = gpio->subdev.device;
0110 u32 inte = nvkm_rd32(device, 0x00e050);
0111 if (type & NVKM_GPIO_LO)
0112 inte = (inte & ~(mask << 16)) | (data << 16);
0113 if (type & NVKM_GPIO_HI)
0114 inte = (inte & ~mask) | data;
0115 nvkm_wr32(device, 0x00e050, inte);
0116 }
0117
0118 static const struct nvkm_gpio_func
0119 nv50_gpio = {
0120 .lines = 16,
0121 .intr_stat = nv50_gpio_intr_stat,
0122 .intr_mask = nv50_gpio_intr_mask,
0123 .drive = nv50_gpio_drive,
0124 .sense = nv50_gpio_sense,
0125 .reset = nv50_gpio_reset,
0126 };
0127
0128 int
0129 nv50_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0130 struct nvkm_gpio **pgpio)
0131 {
0132 return nvkm_gpio_new_(&nv50_gpio, device, type, inst, pgpio);
0133 }