subdev/fb/ramnv40.c

0001 /*
0002  * Copyright 2013 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include "ramnv40.h"
0025
0026 #include <subdev/bios.h>
0027 #include <subdev/bios/bit.h>
0028 #include <subdev/bios/init.h>
0029 #include <subdev/bios/pll.h>
0030 #include <subdev/clk/pll.h>
0031 #include <subdev/timer.h>
0032
0033 static int
0034 nv40_ram_calc(struct nvkm_ram *base, u32 freq)
0035 {
0036     struct nv40_ram *ram = nv40_ram(base);
0037     struct nvkm_subdev *subdev = &ram->base.fb->subdev;
0038     struct nvkm_bios *bios = subdev->device->bios;
0039     struct nvbios_pll pll;
0040     int N1, M1, N2, M2;
0041     int log2P, ret;
0042
0043     ret = nvbios_pll_parse(bios, 0x04, &pll);
0044     if (ret) {
0045         nvkm_error(subdev, "mclk pll data not found\n");
0046         return ret;
0047     }
0048
0049     ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
0050     if (ret < 0)
0051         return ret;
0052
0053     ram->ctrl  = 0x80000000 | (log2P << 16);
0054     ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
0055     if (N2 == M2) {
0056         ram->ctrl |= 0x00000100;
0057         ram->coef  = (N1 << 8) | M1;
0058     } else {
0059         ram->ctrl |= 0x40000000;
0060         ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
0061     }
0062
0063     return 0;
0064 }
0065
0066 static int
0067 nv40_ram_prog(struct nvkm_ram *base)
0068 {
0069     struct nv40_ram *ram = nv40_ram(base);
0070     struct nvkm_subdev *subdev = &ram->base.fb->subdev;
0071     struct nvkm_device *device = subdev->device;
0072     struct nvkm_bios *bios = device->bios;
0073     struct bit_entry M;
0074     u32 crtc_mask = 0;
0075     u8  sr1[2];
0076     int i;
0077
0078     /* determine which CRTCs are active, fetch VGA_SR1 for each */
0079     for (i = 0; i < 2; i++) {
0080         u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000));
0081         u32 cnt = 0;
0082         do {
0083             if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) {
0084                 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
0085                 sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000));
0086                 if (!(sr1[i] & 0x20))
0087                     crtc_mask |= (1 << i);
0088                 break;
0089             }
0090             udelay(1);
0091         } while (cnt++ < 32);
0092     }
0093
0094     /* wait for vblank start on active crtcs, disable memory access */
0095     for (i = 0; i < 2; i++) {
0096         if (!(crtc_mask & (1 << i)))
0097             continue;
0098
0099         nvkm_msec(device, 2000,
0100             u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));
0101             if (!(tmp & 0x00010000))
0102                 break;
0103         );
0104
0105         nvkm_msec(device, 2000,
0106             u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));
0107             if ( (tmp & 0x00010000))
0108                 break;
0109         );
0110
0111         nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
0112         nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
0113     }
0114
0115     /* prepare ram for reclocking */
0116     nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */
0117     nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */
0118     nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */
0119     nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
0120     nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */
0121
0122     /* change the PLL of each memory partition */
0123     nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000);
0124     switch (device->chipset) {
0125     case 0x40:
0126     case 0x45:
0127     case 0x41:
0128     case 0x42:
0129     case 0x47:
0130         nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl);
0131         nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl);
0132         nvkm_wr32(device, 0x004048, ram->coef);
0133         nvkm_wr32(device, 0x004030, ram->coef);
0134         fallthrough;
0135     case 0x43:
0136     case 0x49:
0137     case 0x4b:
0138         nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl);
0139         nvkm_wr32(device, 0x00403c, ram->coef);
0140         fallthrough;
0141     default:
0142         nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl);
0143         nvkm_wr32(device, 0x004024, ram->coef);
0144         break;
0145     }
0146     udelay(100);
0147     nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000);
0148
0149     /* re-enable normal operation of memory controller */
0150     nvkm_wr32(device, 0x1002dc, 0x00000000);
0151     nvkm_mask(device, 0x100210, 0x80000000, 0x80000000);
0152     udelay(100);
0153
0154     /* execute memory reset script from vbios */
0155     if (!bit_entry(bios, 'M', &M))
0156         nvbios_init(subdev, nvbios_rd16(bios, M.offset + 0x00));
0157
0158     /* make sure we're in vblank (hopefully the same one as before), and
0159      * then re-enable crtc memory access
0160      */
0161     for (i = 0; i < 2; i++) {
0162         if (!(crtc_mask & (1 << i)))
0163             continue;
0164
0165         nvkm_msec(device, 2000,
0166             u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));
0167             if ( (tmp & 0x00010000))
0168                 break;
0169         );
0170
0171         nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
0172         nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);
0173     }
0174
0175     return 0;
0176 }
0177
0178 static void
0179 nv40_ram_tidy(struct nvkm_ram *base)
0180 {
0181 }
0182
0183 static const struct nvkm_ram_func
0184 nv40_ram_func = {
0185     .calc = nv40_ram_calc,
0186     .prog = nv40_ram_prog,
0187     .tidy = nv40_ram_tidy,
0188 };
0189
0190 int
0191 nv40_ram_new_(struct nvkm_fb *fb, enum nvkm_ram_type type, u64 size,
0192           struct nvkm_ram **pram)
0193 {
0194     struct nv40_ram *ram;
0195     if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
0196         return -ENOMEM;
0197     *pram = &ram->base;
0198     return nvkm_ram_ctor(&nv40_ram_func, fb, type, size, &ram->base);
0199 }
0200
0201 int
0202 nv40_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
0203 {
0204     struct nvkm_device *device = fb->subdev.device;
0205     u32 pbus1218 = nvkm_rd32(device, 0x001218);
0206     u32     size = nvkm_rd32(device, 0x10020c) & 0xff000000;
0207     enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN;
0208     int ret;
0209
0210     switch (pbus1218 & 0x00000300) {
0211     case 0x00000000: type = NVKM_RAM_TYPE_SDRAM; break;
0212     case 0x00000100: type = NVKM_RAM_TYPE_DDR1 ; break;
0213     case 0x00000200: type = NVKM_RAM_TYPE_GDDR3; break;
0214     case 0x00000300: type = NVKM_RAM_TYPE_DDR2 ; break;
0215     }
0216
0217     ret = nv40_ram_new_(fb, type, size, pram);
0218     if (ret)
0219         return ret;
0220
0221     (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;
0222     return 0;
0223 }