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0001 /*
0002  * Copyright 2013 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #define gf100_ram(p) container_of((p), struct gf100_ram, base)
0025 #include "ram.h"
0026 #include "ramfuc.h"
0027 
0028 #include <core/option.h>
0029 #include <subdev/bios.h>
0030 #include <subdev/bios/pll.h>
0031 #include <subdev/bios/rammap.h>
0032 #include <subdev/bios/timing.h>
0033 #include <subdev/clk.h>
0034 #include <subdev/clk/pll.h>
0035 
0036 struct gf100_ramfuc {
0037     struct ramfuc base;
0038 
0039     struct ramfuc_reg r_0x10fe20;
0040     struct ramfuc_reg r_0x10fe24;
0041     struct ramfuc_reg r_0x137320;
0042     struct ramfuc_reg r_0x137330;
0043 
0044     struct ramfuc_reg r_0x132000;
0045     struct ramfuc_reg r_0x132004;
0046     struct ramfuc_reg r_0x132100;
0047 
0048     struct ramfuc_reg r_0x137390;
0049 
0050     struct ramfuc_reg r_0x10f290;
0051     struct ramfuc_reg r_0x10f294;
0052     struct ramfuc_reg r_0x10f298;
0053     struct ramfuc_reg r_0x10f29c;
0054     struct ramfuc_reg r_0x10f2a0;
0055 
0056     struct ramfuc_reg r_0x10f300;
0057     struct ramfuc_reg r_0x10f338;
0058     struct ramfuc_reg r_0x10f340;
0059     struct ramfuc_reg r_0x10f344;
0060     struct ramfuc_reg r_0x10f348;
0061 
0062     struct ramfuc_reg r_0x10f910;
0063     struct ramfuc_reg r_0x10f914;
0064 
0065     struct ramfuc_reg r_0x100b0c;
0066     struct ramfuc_reg r_0x10f050;
0067     struct ramfuc_reg r_0x10f090;
0068     struct ramfuc_reg r_0x10f200;
0069     struct ramfuc_reg r_0x10f210;
0070     struct ramfuc_reg r_0x10f310;
0071     struct ramfuc_reg r_0x10f314;
0072     struct ramfuc_reg r_0x10f610;
0073     struct ramfuc_reg r_0x10f614;
0074     struct ramfuc_reg r_0x10f800;
0075     struct ramfuc_reg r_0x10f808;
0076     struct ramfuc_reg r_0x10f824;
0077     struct ramfuc_reg r_0x10f830;
0078     struct ramfuc_reg r_0x10f988;
0079     struct ramfuc_reg r_0x10f98c;
0080     struct ramfuc_reg r_0x10f990;
0081     struct ramfuc_reg r_0x10f998;
0082     struct ramfuc_reg r_0x10f9b0;
0083     struct ramfuc_reg r_0x10f9b4;
0084     struct ramfuc_reg r_0x10fb04;
0085     struct ramfuc_reg r_0x10fb08;
0086     struct ramfuc_reg r_0x137300;
0087     struct ramfuc_reg r_0x137310;
0088     struct ramfuc_reg r_0x137360;
0089     struct ramfuc_reg r_0x1373ec;
0090     struct ramfuc_reg r_0x1373f0;
0091     struct ramfuc_reg r_0x1373f8;
0092 
0093     struct ramfuc_reg r_0x61c140;
0094     struct ramfuc_reg r_0x611200;
0095 
0096     struct ramfuc_reg r_0x13d8f4;
0097 };
0098 
0099 struct gf100_ram {
0100     struct nvkm_ram base;
0101     struct gf100_ramfuc fuc;
0102     struct nvbios_pll refpll;
0103     struct nvbios_pll mempll;
0104 };
0105 
0106 static void
0107 gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
0108 {
0109     struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);
0110     struct nvkm_fb *fb = ram->base.fb;
0111     struct nvkm_device *device = fb->subdev.device;
0112     u32 part = nvkm_rd32(device, 0x022438), i;
0113     u32 mask = nvkm_rd32(device, 0x022554);
0114     u32 addr = 0x110974;
0115 
0116     ram_wr32(fuc, 0x10f910, magic);
0117     ram_wr32(fuc, 0x10f914, magic);
0118 
0119     for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
0120         if (mask & (1 << i))
0121             continue;
0122         ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
0123     }
0124 }
0125 
0126 int
0127 gf100_ram_calc(struct nvkm_ram *base, u32 freq)
0128 {
0129     struct gf100_ram *ram = gf100_ram(base);
0130     struct gf100_ramfuc *fuc = &ram->fuc;
0131     struct nvkm_subdev *subdev = &ram->base.fb->subdev;
0132     struct nvkm_device *device = subdev->device;
0133     struct nvkm_clk *clk = device->clk;
0134     struct nvkm_bios *bios = device->bios;
0135     struct nvbios_ramcfg cfg;
0136     u8  ver, cnt, len, strap;
0137     struct {
0138         u32 data;
0139         u8  size;
0140     } rammap, ramcfg, timing;
0141     int ref, div, out;
0142     int from, mode;
0143     int N1, M1, P;
0144     int ret;
0145 
0146     /* lookup memory config data relevant to the target frequency */
0147     rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
0148                       &cnt, &ramcfg.size, &cfg);
0149     if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
0150         nvkm_error(subdev, "invalid/missing rammap entry\n");
0151         return -EINVAL;
0152     }
0153 
0154     /* locate specific data set for the attached memory */
0155     strap = nvbios_ramcfg_index(subdev);
0156     if (strap >= cnt) {
0157         nvkm_error(subdev, "invalid ramcfg strap\n");
0158         return -EINVAL;
0159     }
0160 
0161     ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
0162     if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
0163         nvkm_error(subdev, "invalid/missing ramcfg entry\n");
0164         return -EINVAL;
0165     }
0166 
0167     /* lookup memory timings, if bios says they're present */
0168     strap = nvbios_rd08(bios, ramcfg.data + 0x01);
0169     if (strap != 0xff) {
0170         timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
0171                           &cnt, &len);
0172         if (!timing.data || ver != 0x10 || timing.size < 0x19) {
0173             nvkm_error(subdev, "invalid/missing timing entry\n");
0174             return -EINVAL;
0175         }
0176     } else {
0177         timing.data = 0;
0178     }
0179 
0180     ret = ram_init(fuc, ram->base.fb);
0181     if (ret)
0182         return ret;
0183 
0184     /* determine current mclk configuration */
0185     from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */
0186 
0187     /* determine target mclk configuration */
0188     if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
0189         ref = nvkm_clk_read(clk, nv_clk_src_sppll0);
0190     else
0191         ref = nvkm_clk_read(clk, nv_clk_src_sppll1);
0192     div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
0193     out = (ref * 2) / (div + 2);
0194     mode = freq != out;
0195 
0196     ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
0197 
0198     if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {
0199         ram_nuke(fuc, 0x132000);
0200         ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
0201         ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
0202     }
0203 
0204     if (mode == 1) {
0205         ram_nuke(fuc, 0x10fe20);
0206         ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
0207         ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
0208     }
0209 
0210 // 0x00020034 // 0x0000000a
0211     ram_wr32(fuc, 0x132100, 0x00000001);
0212 
0213     if (mode == 1 && from == 0) {
0214         /* calculate refpll */
0215         ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk,
0216                      &N1, NULL, &M1, &P);
0217         if (ret <= 0) {
0218             nvkm_error(subdev, "unable to calc refpll\n");
0219             return ret ? ret : -ERANGE;
0220         }
0221 
0222         ram_wr32(fuc, 0x10fe20, 0x20010000);
0223         ram_wr32(fuc, 0x137320, 0x00000003);
0224         ram_wr32(fuc, 0x137330, 0x81200006);
0225         ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
0226         ram_wr32(fuc, 0x10fe20, 0x20010001);
0227         ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
0228 
0229         /* calculate mempll */
0230         ret = gt215_pll_calc(subdev, &ram->mempll, freq,
0231                      &N1, NULL, &M1, &P);
0232         if (ret <= 0) {
0233             nvkm_error(subdev, "unable to calc refpll\n");
0234             return ret ? ret : -ERANGE;
0235         }
0236 
0237         ram_wr32(fuc, 0x10fe20, 0x20010005);
0238         ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
0239         ram_wr32(fuc, 0x132000, 0x18010101);
0240         ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
0241     } else
0242     if (mode == 0) {
0243         ram_wr32(fuc, 0x137300, 0x00000003);
0244     }
0245 
0246     if (from == 0) {
0247         ram_nuke(fuc, 0x10fb04);
0248         ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
0249         ram_nuke(fuc, 0x10fb08);
0250         ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
0251         ram_wr32(fuc, 0x10f988, 0x2004ff00);
0252         ram_wr32(fuc, 0x10f98c, 0x003fc040);
0253         ram_wr32(fuc, 0x10f990, 0x20012001);
0254         ram_wr32(fuc, 0x10f998, 0x00011a00);
0255         ram_wr32(fuc, 0x13d8f4, 0x00000000);
0256     } else {
0257         ram_wr32(fuc, 0x10f988, 0x20010000);
0258         ram_wr32(fuc, 0x10f98c, 0x00000000);
0259         ram_wr32(fuc, 0x10f990, 0x20012001);
0260         ram_wr32(fuc, 0x10f998, 0x00010a00);
0261     }
0262 
0263     if (from == 0) {
0264 // 0x00020039 // 0x000000ba
0265     }
0266 
0267 // 0x0002003a // 0x00000002
0268     ram_wr32(fuc, 0x100b0c, 0x00080012);
0269 // 0x00030014 // 0x00000000 // 0x02b5f070
0270 // 0x00030014 // 0x00010000 // 0x02b5f070
0271     ram_wr32(fuc, 0x611200, 0x00003300);
0272 // 0x00020034 // 0x0000000a
0273 // 0x00030020 // 0x00000001 // 0x00000000
0274 
0275     ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
0276     ram_wr32(fuc, 0x10f210, 0x00000000);
0277     ram_nsec(fuc, 1000);
0278     if (mode == 0)
0279         gf100_ram_train(fuc, 0x000c1001);
0280     ram_wr32(fuc, 0x10f310, 0x00000001);
0281     ram_nsec(fuc, 1000);
0282     ram_wr32(fuc, 0x10f090, 0x00000061);
0283     ram_wr32(fuc, 0x10f090, 0xc000007f);
0284     ram_nsec(fuc, 1000);
0285 
0286     if (from == 0) {
0287         ram_wr32(fuc, 0x10f824, 0x00007fd4);
0288     } else {
0289         ram_wr32(fuc, 0x1373ec, 0x00020404);
0290     }
0291 
0292     if (mode == 0) {
0293         ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
0294         ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
0295         ram_wr32(fuc, 0x10f830, 0x41500010);
0296         ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
0297         ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
0298         ram_wr32(fuc, 0x10f050, 0xff000090);
0299         ram_wr32(fuc, 0x1373ec, 0x00020f0f);
0300         ram_wr32(fuc, 0x1373f0, 0x00000003);
0301         ram_wr32(fuc, 0x137310, 0x81201616);
0302         ram_wr32(fuc, 0x132100, 0x00000001);
0303 // 0x00020039 // 0x000000ba
0304         ram_wr32(fuc, 0x10f830, 0x00300017);
0305         ram_wr32(fuc, 0x1373f0, 0x00000001);
0306         ram_wr32(fuc, 0x10f824, 0x00007e77);
0307         ram_wr32(fuc, 0x132000, 0x18030001);
0308         ram_wr32(fuc, 0x10f090, 0x4000007e);
0309         ram_nsec(fuc, 2000);
0310         ram_wr32(fuc, 0x10f314, 0x00000001);
0311         ram_wr32(fuc, 0x10f210, 0x80000000);
0312         ram_wr32(fuc, 0x10f338, 0x00300220);
0313         ram_wr32(fuc, 0x10f300, 0x0000011d);
0314         ram_nsec(fuc, 1000);
0315         ram_wr32(fuc, 0x10f290, 0x02060505);
0316         ram_wr32(fuc, 0x10f294, 0x34208288);
0317         ram_wr32(fuc, 0x10f298, 0x44050411);
0318         ram_wr32(fuc, 0x10f29c, 0x0000114c);
0319         ram_wr32(fuc, 0x10f2a0, 0x42e10069);
0320         ram_wr32(fuc, 0x10f614, 0x40044f77);
0321         ram_wr32(fuc, 0x10f610, 0x40044f77);
0322         ram_wr32(fuc, 0x10f344, 0x00600009);
0323         ram_nsec(fuc, 1000);
0324         ram_wr32(fuc, 0x10f348, 0x00700008);
0325         ram_wr32(fuc, 0x61c140, 0x19240000);
0326         ram_wr32(fuc, 0x10f830, 0x00300017);
0327         gf100_ram_train(fuc, 0x80021001);
0328         gf100_ram_train(fuc, 0x80081001);
0329         ram_wr32(fuc, 0x10f340, 0x00500004);
0330         ram_nsec(fuc, 1000);
0331         ram_wr32(fuc, 0x10f830, 0x01300017);
0332         ram_wr32(fuc, 0x10f830, 0x00300017);
0333 // 0x00030020 // 0x00000000 // 0x00000000
0334 // 0x00020034 // 0x0000000b
0335         ram_wr32(fuc, 0x100b0c, 0x00080028);
0336         ram_wr32(fuc, 0x611200, 0x00003330);
0337     } else {
0338         ram_wr32(fuc, 0x10f800, 0x00001800);
0339         ram_wr32(fuc, 0x13d8f4, 0x00000000);
0340         ram_wr32(fuc, 0x1373ec, 0x00020404);
0341         ram_wr32(fuc, 0x1373f0, 0x00000003);
0342         ram_wr32(fuc, 0x10f830, 0x40700010);
0343         ram_wr32(fuc, 0x10f830, 0x40500010);
0344         ram_wr32(fuc, 0x13d8f4, 0x00000000);
0345         ram_wr32(fuc, 0x1373f8, 0x00000000);
0346         ram_wr32(fuc, 0x132100, 0x00000101);
0347         ram_wr32(fuc, 0x137310, 0x89201616);
0348         ram_wr32(fuc, 0x10f050, 0xff000090);
0349         ram_wr32(fuc, 0x1373ec, 0x00030404);
0350         ram_wr32(fuc, 0x1373f0, 0x00000002);
0351     // 0x00020039 // 0x00000011
0352         ram_wr32(fuc, 0x132100, 0x00000001);
0353         ram_wr32(fuc, 0x1373f8, 0x00002000);
0354         ram_nsec(fuc, 2000);
0355         ram_wr32(fuc, 0x10f808, 0x7aaa0050);
0356         ram_wr32(fuc, 0x10f830, 0x00500010);
0357         ram_wr32(fuc, 0x10f200, 0x00ce1000);
0358         ram_wr32(fuc, 0x10f090, 0x4000007e);
0359         ram_nsec(fuc, 2000);
0360         ram_wr32(fuc, 0x10f314, 0x00000001);
0361         ram_wr32(fuc, 0x10f210, 0x80000000);
0362         ram_wr32(fuc, 0x10f338, 0x00300200);
0363         ram_wr32(fuc, 0x10f300, 0x0000084d);
0364         ram_nsec(fuc, 1000);
0365         ram_wr32(fuc, 0x10f290, 0x0b343825);
0366         ram_wr32(fuc, 0x10f294, 0x3483028e);
0367         ram_wr32(fuc, 0x10f298, 0x440c0600);
0368         ram_wr32(fuc, 0x10f29c, 0x0000214c);
0369         ram_wr32(fuc, 0x10f2a0, 0x42e20069);
0370         ram_wr32(fuc, 0x10f200, 0x00ce0000);
0371         ram_wr32(fuc, 0x10f614, 0x60044e77);
0372         ram_wr32(fuc, 0x10f610, 0x60044e77);
0373         ram_wr32(fuc, 0x10f340, 0x00500000);
0374         ram_nsec(fuc, 1000);
0375         ram_wr32(fuc, 0x10f344, 0x00600228);
0376         ram_nsec(fuc, 1000);
0377         ram_wr32(fuc, 0x10f348, 0x00700000);
0378         ram_wr32(fuc, 0x13d8f4, 0x00000000);
0379         ram_wr32(fuc, 0x61c140, 0x09a40000);
0380 
0381         gf100_ram_train(fuc, 0x800e1008);
0382 
0383         ram_nsec(fuc, 1000);
0384         ram_wr32(fuc, 0x10f800, 0x00001804);
0385     // 0x00030020 // 0x00000000 // 0x00000000
0386     // 0x00020034 // 0x0000000b
0387         ram_wr32(fuc, 0x13d8f4, 0x00000000);
0388         ram_wr32(fuc, 0x100b0c, 0x00080028);
0389         ram_wr32(fuc, 0x611200, 0x00003330);
0390         ram_nsec(fuc, 100000);
0391         ram_wr32(fuc, 0x10f9b0, 0x05313f41);
0392         ram_wr32(fuc, 0x10f9b4, 0x00002f50);
0393 
0394         gf100_ram_train(fuc, 0x010c1001);
0395     }
0396 
0397     ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
0398 // 0x00020016 // 0x00000000
0399 
0400     if (mode == 0)
0401         ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
0402 
0403     return 0;
0404 }
0405 
0406 int
0407 gf100_ram_prog(struct nvkm_ram *base)
0408 {
0409     struct gf100_ram *ram = gf100_ram(base);
0410     struct nvkm_device *device = ram->base.fb->subdev.device;
0411     ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
0412     return 0;
0413 }
0414 
0415 void
0416 gf100_ram_tidy(struct nvkm_ram *base)
0417 {
0418     struct gf100_ram *ram = gf100_ram(base);
0419     ram_exec(&ram->fuc, false);
0420 }
0421 
0422 int
0423 gf100_ram_init(struct nvkm_ram *base)
0424 {
0425     static const u8  train0[] = {
0426         0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,
0427         0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
0428     };
0429     static const u32 train1[] = {
0430         0x00000000, 0xffffffff,
0431         0x55555555, 0xaaaaaaaa,
0432         0x33333333, 0xcccccccc,
0433         0xf0f0f0f0, 0x0f0f0f0f,
0434         0x00ff00ff, 0xff00ff00,
0435         0x0000ffff, 0xffff0000,
0436     };
0437     struct gf100_ram *ram = gf100_ram(base);
0438     struct nvkm_device *device = ram->base.fb->subdev.device;
0439     int i;
0440 
0441     switch (ram->base.type) {
0442     case NVKM_RAM_TYPE_GDDR5:
0443         break;
0444     default:
0445         return 0;
0446     }
0447 
0448     /* prepare for ddr link training, and load training patterns */
0449     for (i = 0; i < 0x30; i++) {
0450         nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8));
0451         nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8));
0452         nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]);
0453         nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]);
0454         nvkm_wr32(device, 0x10f918,              train1[i % 12]);
0455         nvkm_wr32(device, 0x10f91c,              train1[i % 12]);
0456         nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]);
0457         nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]);
0458         nvkm_wr32(device, 0x10f918,              train1[i % 12]);
0459         nvkm_wr32(device, 0x10f91c,              train1[i % 12]);
0460     }
0461 
0462     return 0;
0463 }
0464 
0465 u32
0466 gf100_ram_probe_fbpa_amount(struct nvkm_device *device, int fbpa)
0467 {
0468     return nvkm_rd32(device, 0x11020c + (fbpa * 0x1000));
0469 }
0470 
0471 u32
0472 gf100_ram_probe_fbp_amount(const struct nvkm_ram_func *func, u32 fbpao,
0473                struct nvkm_device *device, int fbp, int *pltcs)
0474 {
0475     if (!(fbpao & BIT(fbp))) {
0476         *pltcs = 1;
0477         return func->probe_fbpa_amount(device, fbp);
0478     }
0479     return 0;
0480 }
0481 
0482 u32
0483 gf100_ram_probe_fbp(const struct nvkm_ram_func *func,
0484             struct nvkm_device *device, int fbp, int *pltcs)
0485 {
0486     u32 fbpao = nvkm_rd32(device, 0x022554);
0487     return func->probe_fbp_amount(func, fbpao, device, fbp, pltcs);
0488 }
0489 
0490 int
0491 gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb,
0492            struct nvkm_ram *ram)
0493 {
0494     struct nvkm_subdev *subdev = &fb->subdev;
0495     struct nvkm_device *device = subdev->device;
0496     struct nvkm_bios *bios = device->bios;
0497     const u32 rsvd_head = ( 256 * 1024); /* vga memory */
0498     const u32 rsvd_tail = (1024 * 1024); /* vbios etc */
0499     enum nvkm_ram_type type = nvkm_fb_bios_memtype(bios);
0500     u32 fbps = nvkm_rd32(device, 0x022438);
0501     u64 total = 0, lcomm = ~0, lower, ubase, usize;
0502     int ret, fbp, ltcs, ltcn = 0;
0503 
0504     nvkm_debug(subdev, "%d FBP(s)\n", fbps);
0505     for (fbp = 0; fbp < fbps; fbp++) {
0506         u32 size = func->probe_fbp(func, device, fbp, &ltcs);
0507         if (size) {
0508             nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
0509                    fbp, size, ltcs);
0510             lcomm  = min(lcomm, (u64)(size / ltcs) << 20);
0511             total += (u64) size << 20;
0512             ltcn  += ltcs;
0513         } else {
0514             nvkm_debug(subdev, "FBP %d: disabled\n", fbp);
0515         }
0516     }
0517 
0518     lower = lcomm * ltcn;
0519     ubase = lcomm + func->upper;
0520     usize = total - lower;
0521 
0522     nvkm_debug(subdev, "Lower: %4lld MiB @ %010llx\n", lower >> 20, 0ULL);
0523     nvkm_debug(subdev, "Upper: %4lld MiB @ %010llx\n", usize >> 20, ubase);
0524     nvkm_debug(subdev, "Total: %4lld MiB\n", total >> 20);
0525 
0526     ret = nvkm_ram_ctor(func, fb, type, total, ram);
0527     if (ret)
0528         return ret;
0529 
0530     nvkm_mm_fini(&ram->vram);
0531 
0532     /* Some GPUs are in what's known as a "mixed memory" configuration.
0533      *
0534      * This is either where some FBPs have more memory than the others,
0535      * or where LTCs have been disabled on a FBP.
0536      */
0537     if (lower != total) {
0538         /* The common memory amount is addressed normally. */
0539         ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
0540                    rsvd_head >> NVKM_RAM_MM_SHIFT,
0541                    (lower - rsvd_head) >> NVKM_RAM_MM_SHIFT, 1);
0542         if (ret)
0543             return ret;
0544 
0545         /* And the rest is much higher in the physical address
0546          * space, and may not be usable for certain operations.
0547          */
0548         ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_MIXED,
0549                    ubase >> NVKM_RAM_MM_SHIFT,
0550                    (usize - rsvd_tail) >> NVKM_RAM_MM_SHIFT, 1);
0551         if (ret)
0552             return ret;
0553     } else {
0554         /* GPUs without mixed-memory are a lot nicer... */
0555         ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
0556                    rsvd_head >> NVKM_RAM_MM_SHIFT,
0557                    (total - rsvd_head - rsvd_tail) >>
0558                    NVKM_RAM_MM_SHIFT, 1);
0559         if (ret)
0560             return ret;
0561     }
0562 
0563     return 0;
0564 }
0565 
0566 int
0567 gf100_ram_new_(const struct nvkm_ram_func *func,
0568            struct nvkm_fb *fb, struct nvkm_ram **pram)
0569 {
0570     struct nvkm_subdev *subdev = &fb->subdev;
0571     struct nvkm_bios *bios = subdev->device->bios;
0572     struct gf100_ram *ram;
0573     int ret;
0574 
0575     if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
0576         return -ENOMEM;
0577     *pram = &ram->base;
0578 
0579     ret = gf100_ram_ctor(func, fb, &ram->base);
0580     if (ret)
0581         return ret;
0582 
0583     ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll);
0584     if (ret) {
0585         nvkm_error(subdev, "mclk refpll data not found\n");
0586         return ret;
0587     }
0588 
0589     ret = nvbios_pll_parse(bios, 0x04, &ram->mempll);
0590     if (ret) {
0591         nvkm_error(subdev, "mclk pll data not found\n");
0592         return ret;
0593     }
0594 
0595     ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20);
0596     ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24);
0597     ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
0598     ram->fuc.r_0x137330 = ramfuc_reg(0x137330);
0599 
0600     ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
0601     ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
0602     ram->fuc.r_0x132100 = ramfuc_reg(0x132100);
0603 
0604     ram->fuc.r_0x137390 = ramfuc_reg(0x137390);
0605 
0606     ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
0607     ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
0608     ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
0609     ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
0610     ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
0611 
0612     ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);
0613     ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);
0614     ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);
0615     ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344);
0616     ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348);
0617 
0618     ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
0619     ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
0620 
0621     ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c);
0622     ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050);
0623     ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
0624     ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
0625     ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
0626     ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
0627     ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
0628     ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
0629     ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
0630     ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
0631     ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
0632     ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
0633     ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
0634     ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988);
0635     ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c);
0636     ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990);
0637     ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998);
0638     ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0);
0639     ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4);
0640     ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04);
0641     ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08);
0642     ram->fuc.r_0x137310 = ramfuc_reg(0x137300);
0643     ram->fuc.r_0x137310 = ramfuc_reg(0x137310);
0644     ram->fuc.r_0x137360 = ramfuc_reg(0x137360);
0645     ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
0646     ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
0647     ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8);
0648 
0649     ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140);
0650     ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
0651 
0652     ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4);
0653     return 0;
0654 }
0655 
0656 static const struct nvkm_ram_func
0657 gf100_ram = {
0658     .upper = 0x0200000000ULL,
0659     .probe_fbp = gf100_ram_probe_fbp,
0660     .probe_fbp_amount = gf100_ram_probe_fbp_amount,
0661     .probe_fbpa_amount = gf100_ram_probe_fbpa_amount,
0662     .init = gf100_ram_init,
0663     .calc = gf100_ram_calc,
0664     .prog = gf100_ram_prog,
0665     .tidy = gf100_ram_tidy,
0666 };
0667 
0668 int
0669 gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
0670 {
0671     return gf100_ram_new_(&gf100_ram, fb, pram);
0672 }
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