subdev/fb/gp102.c

0001 /*
0002  * Copyright 2016 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs <bskeggs@redhat.com>
0023  */
0024 #include "gf100.h"
0025 #include "ram.h"
0026
0027 #include <core/firmware.h>
0028 #include <core/memory.h>
0029 #include <nvfw/fw.h>
0030 #include <nvfw/hs.h>
0031 #include <engine/nvdec.h>
0032
0033 int
0034 gp102_fb_vpr_scrub(struct nvkm_fb *fb)
0035 {
0036     struct nvkm_subdev *subdev = &fb->subdev;
0037     struct nvkm_device *device = subdev->device;
0038     struct nvkm_falcon *falcon = &device->nvdec[0]->falcon;
0039     struct nvkm_blob *blob = &fb->vpr_scrubber;
0040     const struct nvfw_bin_hdr *hsbin_hdr;
0041     const struct nvfw_hs_header *fw_hdr;
0042     const struct nvfw_hs_load_header *lhdr;
0043     void *scrub_data;
0044     u32 patch_loc, patch_sig;
0045     int ret;
0046
0047     nvkm_falcon_get(falcon, subdev);
0048
0049     hsbin_hdr = nvfw_bin_hdr(subdev, blob->data);
0050     fw_hdr = nvfw_hs_header(subdev, blob->data + hsbin_hdr->header_offset);
0051     lhdr = nvfw_hs_load_header(subdev, blob->data + fw_hdr->hdr_offset);
0052     scrub_data = blob->data + hsbin_hdr->data_offset;
0053
0054     patch_loc = *(u32 *)(blob->data + fw_hdr->patch_loc);
0055     patch_sig = *(u32 *)(blob->data + fw_hdr->patch_sig);
0056     if (falcon->debug) {
0057         memcpy(scrub_data + patch_loc,
0058                blob->data + fw_hdr->sig_dbg_offset + patch_sig,
0059                fw_hdr->sig_dbg_size);
0060     } else {
0061         memcpy(scrub_data + patch_loc,
0062                blob->data + fw_hdr->sig_prod_offset + patch_sig,
0063                fw_hdr->sig_prod_size);
0064     }
0065
0066     nvkm_falcon_reset(falcon);
0067     nvkm_falcon_bind_context(falcon, NULL);
0068
0069     nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off,
0070                   lhdr->non_sec_code_size,
0071                   lhdr->non_sec_code_off >> 8, 0, false);
0072     nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0],
0073                   ALIGN(lhdr->apps[0], 0x100),
0074                   lhdr->apps[1],
0075                   lhdr->apps[0] >> 8, 0, true);
0076     nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0,
0077                   lhdr->data_size, 0);
0078
0079     nvkm_falcon_set_start_addr(falcon, 0x0);
0080     nvkm_falcon_start(falcon);
0081
0082     ret = nvkm_falcon_wait_for_halt(falcon, 500);
0083     if (ret < 0) {
0084         ret = -ETIMEDOUT;
0085         goto end;
0086     }
0087
0088     /* put nvdec in clean state - without reset it will remain in HS mode */
0089     nvkm_falcon_reset(falcon);
0090 end:
0091     nvkm_falcon_put(falcon, subdev);
0092     return ret;
0093 }
0094
0095 bool
0096 gp102_fb_vpr_scrub_required(struct nvkm_fb *fb)
0097 {
0098     struct nvkm_device *device = fb->subdev.device;
0099     nvkm_wr32(device, 0x100cd0, 0x2);
0100     return (nvkm_rd32(device, 0x100cd0) & 0x00000010) != 0;
0101 }
0102
0103 static const struct nvkm_fb_func
0104 gp102_fb = {
0105     .dtor = gf100_fb_dtor,
0106     .oneinit = gf100_fb_oneinit,
0107     .init = gp100_fb_init,
0108     .init_remapper = gp100_fb_init_remapper,
0109     .init_page = gm200_fb_init_page,
0110     .vpr.scrub_required = gp102_fb_vpr_scrub_required,
0111     .vpr.scrub = gp102_fb_vpr_scrub,
0112     .ram_new = gp100_ram_new,
0113 };
0114
0115 int
0116 gp102_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
0117           enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
0118 {
0119     int ret = gf100_fb_new_(func, device, type, inst, pfb);
0120     if (ret)
0121         return ret;
0122
0123     nvkm_firmware_load_blob(&(*pfb)->subdev, "nvdec/scrubber", "", 0,
0124                 &(*pfb)->vpr_scrubber);
0125     return 0;
0126 }
0127
0128 int
0129 gp102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
0130 {
0131     return gp102_fb_new_(&gp102_fb, device, type, inst, pfb);
0132 }
0133
0134 MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin");
0135 MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin");
0136 MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin");
0137 MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin");
0138 MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin");