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0025 #include "ram.h"
0026
0027 struct ramxlat {
0028 int id;
0029 u8 enc;
0030 };
0031
0032 static inline int
0033 ramxlat(const struct ramxlat *xlat, int id)
0034 {
0035 while (xlat->id >= 0) {
0036 if (xlat->id == id)
0037 return xlat->enc;
0038 xlat++;
0039 }
0040 return -EINVAL;
0041 }
0042
0043 static const struct ramxlat
0044 ramgddr3_cl_lo[] = {
0045 { 5, 5 }, { 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 }, { 12, 8 },
0046
0047 { 13, 9 }, { 14, 6 },
0048
0049
0050
0051 { -1 }
0052 };
0053
0054 static const struct ramxlat
0055 ramgddr3_cl_hi[] = {
0056 { 10, 2 }, { 11, 3 }, { 12, 4 }, { 13, 5 }, { 14, 6 }, { 15, 7 },
0057 { 16, 0 }, { 17, 1 },
0058 { -1 }
0059 };
0060
0061 static const struct ramxlat
0062 ramgddr3_wr_lo[] = {
0063 { 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 },
0064 { 11, 0 }, { 13 , 1 },
0065
0066 { 4, 0 }, { 6, 3 }, { 12, 1 },
0067 { -1 }
0068 };
0069
0070 int
0071 nvkm_gddr3_calc(struct nvkm_ram *ram)
0072 {
0073 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi;
0074
0075 switch (ram->next->bios.timing_ver) {
0076 case 0x10:
0077 CWL = ram->next->bios.timing_10_CWL;
0078 CL = ram->next->bios.timing_10_CL;
0079 WR = ram->next->bios.timing_10_WR;
0080 DLL = !ram->next->bios.ramcfg_DLLoff;
0081 ODT = ram->next->bios.timing_10_ODT;
0082 RON = ram->next->bios.ramcfg_RON;
0083 break;
0084 case 0x20:
0085 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
0086 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
0087 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
0088
0089 DLL = !(ram->mr[1] & 0x1);
0090 RON = !((ram->mr[1] & 0x300) >> 8);
0091 break;
0092 default:
0093 return -ENOSYS;
0094 }
0095
0096 if (ram->next->bios.timing_ver == 0x20 ||
0097 ram->next->bios.ramcfg_timing == 0xff) {
0098 ODT = (ram->mr[1] & 0xc) >> 2;
0099 }
0100
0101 hi = ram->mr[2] & 0x1;
0102 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL);
0103 WR = ramxlat(ramgddr3_wr_lo, WR);
0104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
0105 return -EINVAL;
0106
0107 ram->mr[0] &= ~0xf74;
0108 ram->mr[0] |= (CWL & 0x07) << 9;
0109 ram->mr[0] |= (CL & 0x07) << 4;
0110 ram->mr[0] |= (CL & 0x08) >> 1;
0111
0112 ram->mr[1] &= ~0x3fc;
0113 ram->mr[1] |= (ODT & 0x03) << 2;
0114 ram->mr[1] |= (RON & 0x03) << 8;
0115 ram->mr[1] |= (WR & 0x03) << 4;
0116 ram->mr[1] |= (WR & 0x04) << 5;
0117 ram->mr[1] |= !DLL << 6;
0118 return 0;
0119 }