subdev/devinit/nv04.c

0001 /*
0002  * Copyright (C) 2010 Francisco Jerez.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining
0006  * a copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sublicense, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the
0014  * next paragraph) shall be included in all copies or substantial
0015  * portions of the Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0018  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0020  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0021  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0022  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0023  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0024  *
0025  */
0026 #include "nv04.h"
0027 #include "fbmem.h"
0028
0029 #include <subdev/bios.h>
0030 #include <subdev/bios/init.h>
0031 #include <subdev/bios/pll.h>
0032 #include <subdev/clk/pll.h>
0033 #include <subdev/vga.h>
0034
0035 static void
0036 nv04_devinit_meminit(struct nvkm_devinit *init)
0037 {
0038     struct nvkm_subdev *subdev = &init->subdev;
0039     struct nvkm_device *device = subdev->device;
0040     u32 patt = 0xdeadbeef;
0041     struct io_mapping *fb;
0042     int i;
0043
0044     /* Map the framebuffer aperture */
0045     fb = fbmem_init(device);
0046     if (!fb) {
0047         nvkm_error(subdev, "failed to map fb\n");
0048         return;
0049     }
0050
0051     /* Sequencer and refresh off */
0052     nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);
0053     nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
0054
0055     nvkm_mask(device, NV04_PFB_BOOT_0, ~0,
0056               NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
0057               NV04_PFB_BOOT_0_RAM_WIDTH_128 |
0058               NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
0059
0060     for (i = 0; i < 4; i++)
0061         fbmem_poke(fb, 4 * i, patt);
0062
0063     fbmem_poke(fb, 0x400000, patt + 1);
0064
0065     if (fbmem_peek(fb, 0) == patt + 1) {
0066         nvkm_mask(device, NV04_PFB_BOOT_0,
0067                   NV04_PFB_BOOT_0_RAM_TYPE,
0068                   NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
0069         nvkm_mask(device, NV04_PFB_DEBUG_0,
0070                   NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
0071
0072         for (i = 0; i < 4; i++)
0073             fbmem_poke(fb, 4 * i, patt);
0074
0075         if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
0076             nvkm_mask(device, NV04_PFB_BOOT_0,
0077                       NV04_PFB_BOOT_0_RAM_WIDTH_128 |
0078                       NV04_PFB_BOOT_0_RAM_AMOUNT,
0079                       NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
0080     } else
0081     if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
0082         nvkm_mask(device, NV04_PFB_BOOT_0,
0083                   NV04_PFB_BOOT_0_RAM_WIDTH_128 |
0084                   NV04_PFB_BOOT_0_RAM_AMOUNT,
0085                   NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
0086     } else
0087     if (fbmem_peek(fb, 0) != patt) {
0088         if (fbmem_readback(fb, 0x800000, patt))
0089             nvkm_mask(device, NV04_PFB_BOOT_0,
0090                       NV04_PFB_BOOT_0_RAM_AMOUNT,
0091                       NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
0092         else
0093             nvkm_mask(device, NV04_PFB_BOOT_0,
0094                       NV04_PFB_BOOT_0_RAM_AMOUNT,
0095                       NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
0096
0097         nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
0098                   NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
0099     } else
0100     if (!fbmem_readback(fb, 0x800000, patt)) {
0101         nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
0102                   NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
0103
0104     }
0105
0106     /* Refresh on, sequencer on */
0107     nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
0108     nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);
0109     fbmem_fini(fb);
0110 }
0111
0112 static int
0113 powerctrl_1_shift(int chip_version, int reg)
0114 {
0115     int shift = -4;
0116
0117     if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
0118         return shift;
0119
0120     switch (reg) {
0121     case 0x680520:
0122         shift += 4; fallthrough;
0123     case 0x680508:
0124         shift += 4; fallthrough;
0125     case 0x680504:
0126         shift += 4; fallthrough;
0127     case 0x680500:
0128         shift += 4;
0129     }
0130
0131     /*
0132      * the shift for vpll regs is only used for nv3x chips with a single
0133      * stage pll
0134      */
0135     if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
0136               chip_version == 0x36 || chip_version >= 0x40))
0137         shift = -4;
0138
0139     return shift;
0140 }
0141
0142 void
0143 setPLL_single(struct nvkm_devinit *init, u32 reg,
0144           struct nvkm_pll_vals *pv)
0145 {
0146     struct nvkm_device *device = init->subdev.device;
0147     int chip_version = device->bios->version.chip;
0148     uint32_t oldpll = nvkm_rd32(device, reg);
0149     int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
0150     uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
0151     uint32_t saved_powerctrl_1 = 0;
0152     int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
0153
0154     if (oldpll == pll)
0155         return; /* already set */
0156
0157     if (shift_powerctrl_1 >= 0) {
0158         saved_powerctrl_1 = nvkm_rd32(device, 0x001584);
0159         nvkm_wr32(device, 0x001584,
0160             (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
0161             1 << shift_powerctrl_1);
0162     }
0163
0164     if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
0165         /* upclock -- write new post divider first */
0166         nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff));
0167     else
0168         /* downclock -- write new NM first */
0169         nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1);
0170
0171     if ((chip_version < 0x17 || chip_version == 0x1a) &&
0172         chip_version != 0x11)
0173         /* wait a bit on older chips */
0174         msleep(64);
0175     nvkm_rd32(device, reg);
0176
0177     /* then write the other half as well */
0178     nvkm_wr32(device, reg, pll);
0179
0180     if (shift_powerctrl_1 >= 0)
0181         nvkm_wr32(device, 0x001584, saved_powerctrl_1);
0182 }
0183
0184 static uint32_t
0185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
0186 {
0187     bool head_a = (reg1 == 0x680508);
0188
0189     if (ss) /* single stage pll mode */
0190         ramdac580 |= head_a ? 0x00000100 : 0x10000000;
0191     else
0192         ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
0193
0194     return ramdac580;
0195 }
0196
0197 void
0198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1,
0199                struct nvkm_pll_vals *pv)
0200 {
0201     struct nvkm_device *device = init->subdev.device;
0202     int chip_version = device->bios->version.chip;
0203     bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
0204     uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
0205     uint32_t oldpll1 = nvkm_rd32(device, reg1);
0206     uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0;
0207     uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
0208     uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
0209     uint32_t oldramdac580 = 0, ramdac580 = 0;
0210     bool single_stage = !pv->NM2 || pv->N2 == pv->M2;   /* nv41+ only */
0211     uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
0212     int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
0213
0214     /* model specific additions to generic pll1 and pll2 set up above */
0215     if (nv3035) {
0216         pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
0217                (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
0218         pll2 = 0;
0219     }
0220     if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
0221         oldramdac580 = nvkm_rd32(device, 0x680580);
0222         ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
0223         if (oldramdac580 != ramdac580)
0224             oldpll1 = ~0;   /* force mismatch */
0225         if (single_stage)
0226             /* magic value used by nvidia in single stage mode */
0227             pll2 |= 0x011f;
0228     }
0229     if (chip_version > 0x70)
0230         /* magic bits set by the blob (but not the bios) on g71-73 */
0231         pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
0232
0233     if (oldpll1 == pll1 && oldpll2 == pll2)
0234         return; /* already set */
0235
0236     if (shift_powerctrl_1 >= 0) {
0237         saved_powerctrl_1 = nvkm_rd32(device, 0x001584);
0238         nvkm_wr32(device, 0x001584,
0239             (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
0240             1 << shift_powerctrl_1);
0241     }
0242
0243     if (chip_version >= 0x40) {
0244         int shift_c040 = 14;
0245
0246         switch (reg1) {
0247         case 0x680504:
0248             shift_c040 += 2; fallthrough;
0249         case 0x680500:
0250             shift_c040 += 2; fallthrough;
0251         case 0x680520:
0252             shift_c040 += 2; fallthrough;
0253         case 0x680508:
0254             shift_c040 += 2;
0255         }
0256
0257         savedc040 = nvkm_rd32(device, 0xc040);
0258         if (shift_c040 != 14)
0259             nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040));
0260     }
0261
0262     if (oldramdac580 != ramdac580)
0263         nvkm_wr32(device, 0x680580, ramdac580);
0264
0265     if (!nv3035)
0266         nvkm_wr32(device, reg2, pll2);
0267     nvkm_wr32(device, reg1, pll1);
0268
0269     if (shift_powerctrl_1 >= 0)
0270         nvkm_wr32(device, 0x001584, saved_powerctrl_1);
0271     if (chip_version >= 0x40)
0272         nvkm_wr32(device, 0xc040, savedc040);
0273 }
0274
0275 void
0276 setPLL_double_lowregs(struct nvkm_devinit *init, u32 NMNMreg,
0277               struct nvkm_pll_vals *pv)
0278 {
0279     /* When setting PLLs, there is a merry game of disabling and enabling
0280      * various bits of hardware during the process. This function is a
0281      * synthesis of six nv4x traces, nearly each card doing a subtly
0282      * different thing. With luck all the necessary bits for each card are
0283      * combined herein. Without luck it deviates from each card's formula
0284      * so as to not work on any :)
0285      */
0286     struct nvkm_device *device = init->subdev.device;
0287     uint32_t Preg = NMNMreg - 4;
0288     bool mpll = Preg == 0x4020;
0289     uint32_t oldPval = nvkm_rd32(device, Preg);
0290     uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
0291     uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
0292             0xc << 28 | pv->log2P << 16;
0293     uint32_t saved4600 = 0;
0294     /* some cards have different maskc040s */
0295     uint32_t maskc040 = ~(3 << 14), savedc040;
0296     bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
0297
0298     if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
0299         return;
0300
0301     if (Preg == 0x4000)
0302         maskc040 = ~0x333;
0303     if (Preg == 0x4058)
0304         maskc040 = ~(0xc << 24);
0305
0306     if (mpll) {
0307         struct nvbios_pll info;
0308         uint8_t Pval2;
0309
0310         if (nvbios_pll_parse(device->bios, Preg, &info))
0311             return;
0312
0313         Pval2 = pv->log2P + info.bias_p;
0314         if (Pval2 > info.max_p)
0315             Pval2 = info.max_p;
0316         Pval |= 1 << 28 | Pval2 << 20;
0317
0318         saved4600 = nvkm_rd32(device, 0x4600);
0319         nvkm_wr32(device, 0x4600, saved4600 | 8 << 28);
0320     }
0321     if (single_stage)
0322         Pval |= mpll ? 1 << 12 : 1 << 8;
0323
0324     nvkm_wr32(device, Preg, oldPval | 1 << 28);
0325     nvkm_wr32(device, Preg, Pval & ~(4 << 28));
0326     if (mpll) {
0327         Pval |= 8 << 20;
0328         nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28));
0329         nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28));
0330     }
0331
0332     savedc040 = nvkm_rd32(device, 0xc040);
0333     nvkm_wr32(device, 0xc040, savedc040 & maskc040);
0334
0335     nvkm_wr32(device, NMNMreg, NMNM);
0336     if (NMNMreg == 0x4024)
0337         nvkm_wr32(device, 0x403c, NMNM);
0338
0339     nvkm_wr32(device, Preg, Pval);
0340     if (mpll) {
0341         Pval &= ~(8 << 20);
0342         nvkm_wr32(device, 0x4020, Pval);
0343         nvkm_wr32(device, 0x4038, Pval);
0344         nvkm_wr32(device, 0x4600, saved4600);
0345     }
0346
0347     nvkm_wr32(device, 0xc040, savedc040);
0348
0349     if (mpll) {
0350         nvkm_wr32(device, 0x4020, Pval & ~(1 << 28));
0351         nvkm_wr32(device, 0x4038, Pval & ~(1 << 28));
0352     }
0353 }
0354
0355 int
0356 nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
0357 {
0358     struct nvkm_subdev *subdev = &devinit->subdev;
0359     struct nvkm_bios *bios = subdev->device->bios;
0360     struct nvkm_pll_vals pv;
0361     struct nvbios_pll info;
0362     int cv = bios->version.chip;
0363     int N1, M1, N2, M2, P;
0364     int ret;
0365
0366     ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
0367     if (ret)
0368         return ret;
0369
0370     ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
0371     if (!ret)
0372         return -EINVAL;
0373
0374     pv.refclk = info.refclk;
0375     pv.N1 = N1;
0376     pv.M1 = M1;
0377     pv.N2 = N2;
0378     pv.M2 = M2;
0379     pv.log2P = P;
0380
0381     if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
0382         cv >= 0x40) {
0383         if (type > 0x405c)
0384             setPLL_double_highregs(devinit, type, &pv);
0385         else
0386             setPLL_double_lowregs(devinit, type, &pv);
0387     } else
0388         setPLL_single(devinit, type, &pv);
0389
0390     return 0;
0391 }
0392
0393 int
0394 nv04_devinit_post(struct nvkm_devinit *init, bool execute)
0395 {
0396     return nvbios_post(&init->subdev, execute);
0397 }
0398
0399 void
0400 nv04_devinit_preinit(struct nvkm_devinit *base)
0401 {
0402     struct nv04_devinit *init = nv04_devinit(base);
0403     struct nvkm_subdev *subdev = &init->base.subdev;
0404     struct nvkm_device *device = subdev->device;
0405
0406     /* make i2c busses accessible */
0407     nvkm_mask(device, 0x000200, 0x00000001, 0x00000001);
0408
0409     /* unslave crtcs */
0410     if (init->owner < 0)
0411         init->owner = nvkm_rdvgaowner(device);
0412     nvkm_wrvgaowner(device, 0);
0413
0414     if (!init->base.post) {
0415         u32 htotal = nvkm_rdvgac(device, 0, 0x06);
0416         htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8;
0417         htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4;
0418         htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10;
0419         htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11;
0420         if (!htotal) {
0421             nvkm_debug(subdev, "adaptor not initialised\n");
0422             init->base.post = true;
0423         }
0424     }
0425 }
0426
0427 void *
0428 nv04_devinit_dtor(struct nvkm_devinit *base)
0429 {
0430     struct nv04_devinit *init = nv04_devinit(base);
0431     /* restore vga owner saved at first init */
0432     nvkm_wrvgaowner(init->base.subdev.device, init->owner);
0433     return init;
0434 }
0435
0436 int
0437 nv04_devinit_new_(const struct nvkm_devinit_func *func, struct nvkm_device *device,
0438           enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit)
0439 {
0440     struct nv04_devinit *init;
0441
0442     if (!(init = kzalloc(sizeof(*init), GFP_KERNEL)))
0443         return -ENOMEM;
0444     *pinit = &init->base;
0445
0446     nvkm_devinit_ctor(func, device, type, inst, &init->base);
0447     init->owner = -1;
0448     return 0;
0449 }
0450
0451 static const struct nvkm_devinit_func
0452 nv04_devinit = {
0453     .dtor = nv04_devinit_dtor,
0454     .preinit = nv04_devinit_preinit,
0455     .post = nv04_devinit_post,
0456     .meminit = nv04_devinit_meminit,
0457     .pll_set = nv04_devinit_pll_set,
0458 };
0459
0460 int
0461 nv04_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0462          struct nvkm_devinit **pinit)
0463 {
0464     return nv04_devinit_new_(&nv04_devinit, device, type, inst, pinit);
0465 }