subdev/clk/nv50.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NV50_CLK_H__
0003 #define __NV50_CLK_H__
0004 #define nv50_clk(p) container_of((p), struct nv50_clk, base)
0005 #include "priv.h"
0006
0007 #include <subdev/bus/hwsq.h>
0008
0009 struct nv50_clk_hwsq {
0010     struct hwsq base;
0011     struct hwsq_reg r_fifo;
0012     struct hwsq_reg r_spll[2];
0013     struct hwsq_reg r_nvpll[2];
0014     struct hwsq_reg r_divs;
0015     struct hwsq_reg r_mast;
0016 };
0017
0018 struct nv50_clk {
0019     struct nvkm_clk base;
0020     struct nv50_clk_hwsq hwsq;
0021 };
0022
0023 int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
0024           bool, struct nvkm_clk **);
0025 int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src);
0026 int nv50_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
0027 int nv50_clk_prog(struct nvkm_clk *);
0028 void nv50_clk_tidy(struct nvkm_clk *);
0029 #endif