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0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include "nv50.h"
0025 #include "pll.h"
0026 #include "seq.h"
0027 
0028 #include <subdev/bios.h>
0029 #include <subdev/bios/pll.h>
0030 
0031 static u32
0032 read_div(struct nv50_clk *clk)
0033 {
0034     struct nvkm_device *device = clk->base.subdev.device;
0035     switch (device->chipset) {
0036     case 0x50: /* it exists, but only has bit 31, not the dividers.. */
0037     case 0x84:
0038     case 0x86:
0039     case 0x98:
0040     case 0xa0:
0041         return nvkm_rd32(device, 0x004700);
0042     case 0x92:
0043     case 0x94:
0044     case 0x96:
0045         return nvkm_rd32(device, 0x004800);
0046     default:
0047         return 0x00000000;
0048     }
0049 }
0050 
0051 static u32
0052 read_pll_src(struct nv50_clk *clk, u32 base)
0053 {
0054     struct nvkm_subdev *subdev = &clk->base.subdev;
0055     struct nvkm_device *device = subdev->device;
0056     u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);
0057     u32 rsel = nvkm_rd32(device, 0x00e18c);
0058     int P, N, M, id;
0059 
0060     switch (device->chipset) {
0061     case 0x50:
0062     case 0xa0:
0063         switch (base) {
0064         case 0x4020:
0065         case 0x4028: id = !!(rsel & 0x00000004); break;
0066         case 0x4008: id = !!(rsel & 0x00000008); break;
0067         case 0x4030: id = 0; break;
0068         default:
0069             nvkm_error(subdev, "ref: bad pll %06x\n", base);
0070             return 0;
0071         }
0072 
0073         coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c));
0074         ref *=  (coef & 0x01000000) ? 2 : 4;
0075         P    =  (coef & 0x00070000) >> 16;
0076         N    = ((coef & 0x0000ff00) >> 8) + 1;
0077         M    = ((coef & 0x000000ff) >> 0) + 1;
0078         break;
0079     case 0x84:
0080     case 0x86:
0081     case 0x92:
0082         coef = nvkm_rd32(device, 0x00e81c);
0083         P    = (coef & 0x00070000) >> 16;
0084         N    = (coef & 0x0000ff00) >> 8;
0085         M    = (coef & 0x000000ff) >> 0;
0086         break;
0087     case 0x94:
0088     case 0x96:
0089     case 0x98:
0090         rsel = nvkm_rd32(device, 0x00c050);
0091         switch (base) {
0092         case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
0093         case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
0094         case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
0095         case 0x4030: rsel = 3; break;
0096         default:
0097             nvkm_error(subdev, "ref: bad pll %06x\n", base);
0098             return 0;
0099         }
0100 
0101         switch (rsel) {
0102         case 0: id = 1; break;
0103         case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);
0104         case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);
0105         case 3: id = 0; break;
0106         }
0107 
0108         coef =  nvkm_rd32(device, 0x00e81c + (id * 0x28));
0109         P    = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7;
0110         P   += (coef & 0x00070000) >> 16;
0111         N    = (coef & 0x0000ff00) >> 8;
0112         M    = (coef & 0x000000ff) >> 0;
0113         break;
0114     default:
0115         BUG();
0116     }
0117 
0118     if (M)
0119         return (ref * N / M) >> P;
0120 
0121     return 0;
0122 }
0123 
0124 static u32
0125 read_pll_ref(struct nv50_clk *clk, u32 base)
0126 {
0127     struct nvkm_subdev *subdev = &clk->base.subdev;
0128     struct nvkm_device *device = subdev->device;
0129     u32 src, mast = nvkm_rd32(device, 0x00c040);
0130 
0131     switch (base) {
0132     case 0x004028:
0133         src = !!(mast & 0x00200000);
0134         break;
0135     case 0x004020:
0136         src = !!(mast & 0x00400000);
0137         break;
0138     case 0x004008:
0139         src = !!(mast & 0x00010000);
0140         break;
0141     case 0x004030:
0142         src = !!(mast & 0x02000000);
0143         break;
0144     case 0x00e810:
0145         return nvkm_clk_read(&clk->base, nv_clk_src_crystal);
0146     default:
0147         nvkm_error(subdev, "bad pll %06x\n", base);
0148         return 0;
0149     }
0150 
0151     if (src)
0152         return nvkm_clk_read(&clk->base, nv_clk_src_href);
0153 
0154     return read_pll_src(clk, base);
0155 }
0156 
0157 static u32
0158 read_pll(struct nv50_clk *clk, u32 base)
0159 {
0160     struct nvkm_device *device = clk->base.subdev.device;
0161     u32 mast = nvkm_rd32(device, 0x00c040);
0162     u32 ctrl = nvkm_rd32(device, base + 0);
0163     u32 coef = nvkm_rd32(device, base + 4);
0164     u32 ref = read_pll_ref(clk, base);
0165     u32 freq = 0;
0166     int N1, N2, M1, M2;
0167 
0168     if (base == 0x004028 && (mast & 0x00100000)) {
0169         /* wtf, appears to only disable post-divider on gt200 */
0170         if (device->chipset != 0xa0)
0171             return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
0172     }
0173 
0174     N2 = (coef & 0xff000000) >> 24;
0175     M2 = (coef & 0x00ff0000) >> 16;
0176     N1 = (coef & 0x0000ff00) >> 8;
0177     M1 = (coef & 0x000000ff);
0178     if ((ctrl & 0x80000000) && M1) {
0179         freq = ref * N1 / M1;
0180         if ((ctrl & 0x40000100) == 0x40000000) {
0181             if (M2)
0182                 freq = freq * N2 / M2;
0183             else
0184                 freq = 0;
0185         }
0186     }
0187 
0188     return freq;
0189 }
0190 
0191 int
0192 nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
0193 {
0194     struct nv50_clk *clk = nv50_clk(base);
0195     struct nvkm_subdev *subdev = &clk->base.subdev;
0196     struct nvkm_device *device = subdev->device;
0197     u32 mast = nvkm_rd32(device, 0x00c040);
0198     u32 P = 0;
0199 
0200     switch (src) {
0201     case nv_clk_src_crystal:
0202         return device->crystal;
0203     case nv_clk_src_href:
0204         return 100000; /* PCIE reference clock */
0205     case nv_clk_src_hclk:
0206         return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);
0207     case nv_clk_src_hclkm3:
0208         return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;
0209     case nv_clk_src_hclkm3d2:
0210         return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;
0211     case nv_clk_src_host:
0212         switch (mast & 0x30000000) {
0213         case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
0214         case 0x10000000: break;
0215         case 0x20000000: /* !0x50 */
0216         case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
0217         }
0218         break;
0219     case nv_clk_src_core:
0220         if (!(mast & 0x00100000))
0221             P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16;
0222         switch (mast & 0x00000003) {
0223         case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
0224         case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
0225         case 0x00000002: return read_pll(clk, 0x004020) >> P;
0226         case 0x00000003: return read_pll(clk, 0x004028) >> P;
0227         }
0228         break;
0229     case nv_clk_src_shader:
0230         P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16;
0231         switch (mast & 0x00000030) {
0232         case 0x00000000:
0233             if (mast & 0x00000080)
0234                 return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;
0235             return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
0236         case 0x00000010: break;
0237         case 0x00000020: return read_pll(clk, 0x004028) >> P;
0238         case 0x00000030: return read_pll(clk, 0x004020) >> P;
0239         }
0240         break;
0241     case nv_clk_src_mem:
0242         P = (nvkm_rd32(device, 0x004008) & 0x00070000) >> 16;
0243         if (nvkm_rd32(device, 0x004008) & 0x00000200) {
0244             switch (mast & 0x0000c000) {
0245             case 0x00000000:
0246                 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
0247             case 0x00008000:
0248             case 0x0000c000:
0249                 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;
0250             }
0251         } else {
0252             return read_pll(clk, 0x004008) >> P;
0253         }
0254         break;
0255     case nv_clk_src_vdec:
0256         P = (read_div(clk) & 0x00000700) >> 8;
0257         switch (device->chipset) {
0258         case 0x84:
0259         case 0x86:
0260         case 0x92:
0261         case 0x94:
0262         case 0x96:
0263         case 0xa0:
0264             switch (mast & 0x00000c00) {
0265             case 0x00000000:
0266                 if (device->chipset == 0xa0) /* wtf?? */
0267                     return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
0268                 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
0269             case 0x00000400:
0270                 return 0;
0271             case 0x00000800:
0272                 if (mast & 0x01000000)
0273                     return read_pll(clk, 0x004028) >> P;
0274                 return read_pll(clk, 0x004030) >> P;
0275             case 0x00000c00:
0276                 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
0277             }
0278             break;
0279         case 0x98:
0280             switch (mast & 0x00000c00) {
0281             case 0x00000000:
0282                 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
0283             case 0x00000400:
0284                 return 0;
0285             case 0x00000800:
0286                 return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;
0287             case 0x00000c00:
0288                 return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;
0289             }
0290             break;
0291         }
0292         break;
0293     case nv_clk_src_dom6:
0294         switch (device->chipset) {
0295         case 0x50:
0296         case 0xa0:
0297             return read_pll(clk, 0x00e810) >> 2;
0298         case 0x84:
0299         case 0x86:
0300         case 0x92:
0301         case 0x94:
0302         case 0x96:
0303         case 0x98:
0304             P = (read_div(clk) & 0x00000007) >> 0;
0305             switch (mast & 0x0c000000) {
0306             case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
0307             case 0x04000000: break;
0308             case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
0309             case 0x0c000000:
0310                 return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;
0311             }
0312             break;
0313         default:
0314             break;
0315         }
0316         break;
0317     default:
0318         break;
0319     }
0320 
0321     nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
0322     return -EINVAL;
0323 }
0324 
0325 static u32
0326 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
0327 {
0328     struct nvkm_subdev *subdev = &clk->base.subdev;
0329     struct nvbios_pll pll;
0330     int ret;
0331 
0332     ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
0333     if (ret)
0334         return 0;
0335 
0336     pll.vco2.max_freq = 0;
0337     pll.refclk = read_pll_ref(clk, reg);
0338     if (!pll.refclk)
0339         return 0;
0340 
0341     return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P);
0342 }
0343 
0344 static inline u32
0345 calc_div(u32 src, u32 target, int *div)
0346 {
0347     u32 clk0 = src, clk1 = src;
0348     for (*div = 0; *div <= 7; (*div)++) {
0349         if (clk0 <= target) {
0350             clk1 = clk0 << (*div ? 1 : 0);
0351             break;
0352         }
0353         clk0 >>= 1;
0354     }
0355 
0356     if (target - clk0 <= clk1 - target)
0357         return clk0;
0358     (*div)--;
0359     return clk1;
0360 }
0361 
0362 static inline u32
0363 clk_same(u32 a, u32 b)
0364 {
0365     return ((a / 1000) == (b / 1000));
0366 }
0367 
0368 int
0369 nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
0370 {
0371     struct nv50_clk *clk = nv50_clk(base);
0372     struct nv50_clk_hwsq *hwsq = &clk->hwsq;
0373     struct nvkm_subdev *subdev = &clk->base.subdev;
0374     struct nvkm_device *device = subdev->device;
0375     const int shader = cstate->domain[nv_clk_src_shader];
0376     const int core = cstate->domain[nv_clk_src_core];
0377     const int vdec = cstate->domain[nv_clk_src_vdec];
0378     const int dom6 = cstate->domain[nv_clk_src_dom6];
0379     u32 mastm = 0, mastv = 0;
0380     u32 divsm = 0, divsv = 0;
0381     int N, M, P1, P2;
0382     int freq, out;
0383 
0384     /* prepare a hwsq script from which we'll perform the reclock */
0385     out = clk_init(hwsq, subdev);
0386     if (out)
0387         return out;
0388 
0389     clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
0390     clk_nsec(hwsq, 8000);
0391     clk_setf(hwsq, 0x10, 0x00); /* disable fb */
0392     clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
0393 
0394     /* vdec: avoid modifying xpll until we know exactly how the other
0395      * clock domains work, i suspect at least some of them can also be
0396      * tied to xpll...
0397      */
0398     if (vdec) {
0399         /* see how close we can get using nvclk as a source */
0400         freq = calc_div(core, vdec, &P1);
0401 
0402         /* see how close we can get using xpll/hclk as a source */
0403         if (device->chipset != 0x98)
0404             out = read_pll(clk, 0x004030);
0405         else
0406             out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);
0407         out = calc_div(out, vdec, &P2);
0408 
0409         /* select whichever gets us closest */
0410         if (abs(vdec - freq) <= abs(vdec - out)) {
0411             if (device->chipset != 0x98)
0412                 mastv |= 0x00000c00;
0413             divsv |= P1 << 8;
0414         } else {
0415             mastv |= 0x00000800;
0416             divsv |= P2 << 8;
0417         }
0418 
0419         mastm |= 0x00000c00;
0420         divsm |= 0x00000700;
0421     }
0422 
0423     /* dom6: nfi what this is, but we're limited to various combinations
0424      * of the host clock frequency
0425      */
0426     if (dom6) {
0427         if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {
0428             mastv |= 0x00000000;
0429         } else
0430         if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {
0431             mastv |= 0x08000000;
0432         } else {
0433             freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;
0434             calc_div(freq, dom6, &P1);
0435 
0436             mastv |= 0x0c000000;
0437             divsv |= P1;
0438         }
0439 
0440         mastm |= 0x0c000000;
0441         divsm |= 0x00000007;
0442     }
0443 
0444     /* vdec/dom6: switch to "safe" clocks temporarily, update dividers
0445      * and then switch to target clocks
0446      */
0447     clk_mask(hwsq, mast, mastm, 0x00000000);
0448     clk_mask(hwsq, divs, divsm, divsv);
0449     clk_mask(hwsq, mast, mastm, mastv);
0450 
0451     /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
0452      * sclk to hclk) before reprogramming
0453      */
0454     if (device->chipset < 0x92)
0455         clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
0456     else
0457         clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
0458 
0459     /* core: for the moment at least, always use nvpll */
0460     freq = calc_pll(clk, 0x4028, core, &N, &M, &P1);
0461     if (freq == 0)
0462         return -ERANGE;
0463 
0464     clk_mask(hwsq, nvpll[0], 0xc03f0100,
0465                  0x80000000 | (P1 << 19) | (P1 << 16));
0466     clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
0467 
0468     /* shader: tie to nvclk if possible, otherwise use spll.  have to be
0469      * very careful that the shader clock is at least twice the core, or
0470      * some chipsets will be very unhappy.  i expect most or all of these
0471      * cases will be handled by tying to nvclk, but it's possible there's
0472      * corners
0473      */
0474     if (P1-- && shader == (core << 1)) {
0475         clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
0476         clk_mask(hwsq, mast, 0x00100033, 0x00000023);
0477     } else {
0478         freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
0479         if (freq == 0)
0480             return -ERANGE;
0481 
0482         clk_mask(hwsq, spll[0], 0xc03f0100,
0483                     0x80000000 | (P1 << 19) | (P1 << 16));
0484         clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
0485         clk_mask(hwsq, mast, 0x00100033, 0x00000033);
0486     }
0487 
0488     /* restore normal operation */
0489     clk_setf(hwsq, 0x10, 0x01); /* enable fb */
0490     clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
0491     clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
0492     return 0;
0493 }
0494 
0495 int
0496 nv50_clk_prog(struct nvkm_clk *base)
0497 {
0498     struct nv50_clk *clk = nv50_clk(base);
0499     return clk_exec(&clk->hwsq, true);
0500 }
0501 
0502 void
0503 nv50_clk_tidy(struct nvkm_clk *base)
0504 {
0505     struct nv50_clk *clk = nv50_clk(base);
0506     clk_exec(&clk->hwsq, false);
0507 }
0508 
0509 int
0510 nv50_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
0511           enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
0512 {
0513     struct nv50_clk *clk;
0514     int ret;
0515 
0516     if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
0517         return -ENOMEM;
0518     ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base);
0519     *pclk = &clk->base;
0520     if (ret)
0521         return ret;
0522 
0523     clk->hwsq.r_fifo = hwsq_reg(0x002504);
0524     clk->hwsq.r_spll[0] = hwsq_reg(0x004020);
0525     clk->hwsq.r_spll[1] = hwsq_reg(0x004024);
0526     clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
0527     clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
0528     switch (device->chipset) {
0529     case 0x92:
0530     case 0x94:
0531     case 0x96:
0532         clk->hwsq.r_divs = hwsq_reg(0x004800);
0533         break;
0534     default:
0535         clk->hwsq.r_divs = hwsq_reg(0x004700);
0536         break;
0537     }
0538     clk->hwsq.r_mast = hwsq_reg(0x00c040);
0539     return 0;
0540 }
0541 
0542 static const struct nvkm_clk_func
0543 nv50_clk = {
0544     .read = nv50_clk_read,
0545     .calc = nv50_clk_calc,
0546     .prog = nv50_clk_prog,
0547     .tidy = nv50_clk_tidy,
0548     .domains = {
0549         { nv_clk_src_crystal, 0xff },
0550         { nv_clk_src_href   , 0xff },
0551         { nv_clk_src_core   , 0xff, 0, "core", 1000 },
0552         { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
0553         { nv_clk_src_mem    , 0xff, 0, "memory", 1000 },
0554         { nv_clk_src_max }
0555     }
0556 };
0557 
0558 int
0559 nv50_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0560          struct nvkm_clk **pclk)
0561 {
0562     return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk);
0563 }
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