subdev/clk/gk20a.h

0001 /*
0002  * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0019  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0020  * DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __NVKM_CLK_GK20A_H__
0025 #define __NVKM_CLK_GK20A_H__
0026
0027 #define KHZ (1000)
0028 #define MHZ (KHZ * 1000)
0029
0030 #define MASK(w) ((1 << (w)) - 1)
0031
0032 #define GK20A_CLK_GPC_MDIV 1000
0033
0034 #define SYS_GPCPLL_CFG_BASE 0x00137000
0035 #define GPCPLL_CFG      (SYS_GPCPLL_CFG_BASE + 0)
0036 #define GPCPLL_CFG_ENABLE   BIT(0)
0037 #define GPCPLL_CFG_IDDQ     BIT(1)
0038 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4)
0039 #define GPCPLL_CFG_LOCK     BIT(17)
0040
0041 #define GPCPLL_CFG2     (SYS_GPCPLL_CFG_BASE + 0xc)
0042 #define GPCPLL_CFG2_SETUP2_SHIFT    16
0043 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24
0044
0045 #define GPCPLL_CFG3         (SYS_GPCPLL_CFG_BASE + 0x18)
0046 #define GPCPLL_CFG3_VCO_CTRL_SHIFT      0
0047 #define GPCPLL_CFG3_VCO_CTRL_WIDTH      9
0048 #define GPCPLL_CFG3_VCO_CTRL_MASK       \
0049     (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
0050 #define GPCPLL_CFG3_PLL_STEPB_SHIFT     16
0051 #define GPCPLL_CFG3_PLL_STEPB_WIDTH     8
0052
0053 #define GPCPLL_COEFF        (SYS_GPCPLL_CFG_BASE + 4)
0054 #define GPCPLL_COEFF_M_SHIFT    0
0055 #define GPCPLL_COEFF_M_WIDTH    8
0056 #define GPCPLL_COEFF_N_SHIFT    8
0057 #define GPCPLL_COEFF_N_WIDTH    8
0058 #define GPCPLL_COEFF_N_MASK \
0059     (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
0060 #define GPCPLL_COEFF_P_SHIFT    16
0061 #define GPCPLL_COEFF_P_WIDTH    6
0062
0063 #define GPCPLL_NDIV_SLOWDOWN            (SYS_GPCPLL_CFG_BASE + 0x1c)
0064 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT  0
0065 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8
0066 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16
0067 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT   22
0068 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT   31
0069
0070 #define GPC_BCAST_GPCPLL_CFG_BASE       0x00132800
0071 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG   (GPC_BCAST_GPCPLL_CFG_BASE + 0xa0)
0072 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24
0073 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
0074     (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
0075
0076 #define SEL_VCO             (SYS_GPCPLL_CFG_BASE + 0x100)
0077 #define SEL_VCO_GPC2CLK_OUT_SHIFT   0
0078
0079 #define GPC2CLK_OUT         (SYS_GPCPLL_CFG_BASE + 0x250)
0080 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1
0081 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31
0082 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE  1
0083 #define GPC2CLK_OUT_VCODIV_WIDTH    6
0084 #define GPC2CLK_OUT_VCODIV_SHIFT    8
0085 #define GPC2CLK_OUT_VCODIV1     0
0086 #define GPC2CLK_OUT_VCODIV2     2
0087 #define GPC2CLK_OUT_VCODIV_MASK     (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
0088                     GPC2CLK_OUT_VCODIV_SHIFT)
0089 #define GPC2CLK_OUT_BYPDIV_WIDTH    6
0090 #define GPC2CLK_OUT_BYPDIV_SHIFT    0
0091 #define GPC2CLK_OUT_BYPDIV31        0x3c
0092 #define GPC2CLK_OUT_INIT_MASK   ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
0093         GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
0094         | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
0095         | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
0096 #define GPC2CLK_OUT_INIT_VAL    ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
0097         GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
0098         | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
0099         | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
0100
0101 /* All frequencies in Khz */
0102 struct gk20a_clk_pllg_params {
0103     u32 min_vco, max_vco;
0104     u32 min_u, max_u;
0105     u32 min_m, max_m;
0106     u32 min_n, max_n;
0107     u32 min_pl, max_pl;
0108 };
0109
0110 struct gk20a_pll {
0111     u32 m;
0112     u32 n;
0113     u32 pl;
0114 };
0115
0116 struct gk20a_clk {
0117     struct nvkm_clk base;
0118     const struct gk20a_clk_pllg_params *params;
0119     struct gk20a_pll pll;
0120     u32 parent_rate;
0121
0122     u32 (*div_to_pl)(u32);
0123     u32 (*pl_to_div)(u32);
0124 };
0125 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
0126
0127 u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *);
0128 int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *);
0129 void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *);
0130 void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *);
0131
0132 static inline bool
0133 gk20a_pllg_is_enabled(struct gk20a_clk *clk)
0134 {
0135     struct nvkm_device *device = clk->base.subdev.device;
0136     u32 val;
0137
0138     val = nvkm_rd32(device, GPCPLL_CFG);
0139     return val & GPCPLL_CFG_ENABLE;
0140 }
0141
0142 static inline u32
0143 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
0144 {
0145     return DIV_ROUND_UP(pll->m * clk->params->min_vco,
0146                 clk->parent_rate / KHZ);
0147 }
0148
0149 int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *,
0150            const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
0151 void gk20a_clk_fini(struct nvkm_clk *);
0152 int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);
0153 int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
0154 int gk20a_clk_prog(struct nvkm_clk *);
0155 void gk20a_clk_tidy(struct nvkm_clk *);
0156
0157 int gk20a_clk_setup_slide(struct gk20a_clk *);
0158
0159 #endif