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0025 #include "priv.h"
0026
0027 #include <subdev/gpio.h>
0028 #include <subdev/therm.h>
0029
0030 static void
0031 nv31_bus_intr(struct nvkm_bus *bus)
0032 {
0033 struct nvkm_subdev *subdev = &bus->subdev;
0034 struct nvkm_device *device = subdev->device;
0035 u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
0036 u32 gpio = nvkm_rd32(device, 0x001104) & nvkm_rd32(device, 0x001144);
0037
0038 if (gpio) {
0039 struct nvkm_gpio *gpio = device->gpio;
0040 if (gpio)
0041 nvkm_subdev_intr(&gpio->subdev);
0042 }
0043
0044 if (stat & 0x00000008) {
0045 u32 addr = nvkm_rd32(device, 0x009084);
0046 u32 data = nvkm_rd32(device, 0x009088);
0047
0048 nvkm_error_ratelimited(subdev, "MMIO %s of %08x FAULT at %06x\n",
0049 (addr & 0x00000002) ? "write" : "read", data,
0050 (addr & 0x00fffffc));
0051
0052 stat &= ~0x00000008;
0053 nvkm_wr32(device, 0x001100, 0x00000008);
0054 }
0055
0056 if (stat & 0x00070000) {
0057 struct nvkm_therm *therm = device->therm;
0058 if (therm)
0059 nvkm_subdev_intr(&therm->subdev);
0060 stat &= ~0x00070000;
0061 nvkm_wr32(device, 0x001100, 0x00070000);
0062 }
0063
0064 if (stat) {
0065 nvkm_error(subdev, "intr %08x\n", stat);
0066 nvkm_mask(device, 0x001140, stat, 0x00000000);
0067 }
0068 }
0069
0070 static void
0071 nv31_bus_init(struct nvkm_bus *bus)
0072 {
0073 struct nvkm_device *device = bus->subdev.device;
0074 nvkm_wr32(device, 0x001100, 0xffffffff);
0075 nvkm_wr32(device, 0x001140, 0x00070008);
0076 }
0077
0078 static const struct nvkm_bus_func
0079 nv31_bus = {
0080 .init = nv31_bus_init,
0081 .intr = nv31_bus_intr,
0082 };
0083
0084 int
0085 nv31_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0086 struct nvkm_bus **pbus)
0087 {
0088 return nvkm_bus_new_(&nv31_bus, device, type, inst, pbus);
0089 }