subdev/bios/timing.c

0001 /*
0002  * Copyright 2013 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include <subdev/bios.h>
0025 #include <subdev/bios/bit.h>
0026 #include <subdev/bios/timing.h>
0027
0028 u32
0029 nvbios_timingTe(struct nvkm_bios *bios,
0030         u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
0031 {
0032     struct bit_entry bit_P;
0033     u32 timing = 0;
0034
0035     if (!bit_entry(bios, 'P', &bit_P)) {
0036         if (bit_P.version == 1)
0037             timing = nvbios_rd32(bios, bit_P.offset + 4);
0038         else
0039         if (bit_P.version == 2)
0040             timing = nvbios_rd32(bios, bit_P.offset + 8);
0041
0042         if (timing) {
0043             *ver = nvbios_rd08(bios, timing + 0);
0044             switch (*ver) {
0045             case 0x10:
0046                 *hdr = nvbios_rd08(bios, timing + 1);
0047                 *cnt = nvbios_rd08(bios, timing + 2);
0048                 *len = nvbios_rd08(bios, timing + 3);
0049                 *snr = 0;
0050                 *ssz = 0;
0051                 return timing;
0052             case 0x20:
0053                 *hdr = nvbios_rd08(bios, timing + 1);
0054                 *cnt = nvbios_rd08(bios, timing + 5);
0055                 *len = nvbios_rd08(bios, timing + 2);
0056                 *snr = nvbios_rd08(bios, timing + 4);
0057                 *ssz = nvbios_rd08(bios, timing + 3);
0058                 return timing;
0059             default:
0060                 break;
0061             }
0062         }
0063     }
0064
0065     return 0;
0066 }
0067
0068 u32
0069 nvbios_timingEe(struct nvkm_bios *bios, int idx,
0070         u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
0071 {
0072     u8  snr, ssz;
0073     u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
0074     if (timing && idx < *cnt) {
0075         timing += *hdr + idx * (*len + (snr * ssz));
0076         *hdr = *len;
0077         *cnt = snr;
0078         *len = ssz;
0079         return timing;
0080     }
0081     return 0;
0082 }
0083
0084 u32
0085 nvbios_timingEp(struct nvkm_bios *bios, int idx,
0086         u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
0087 {
0088     u32 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
0089     p->timing_ver = *ver;
0090     p->timing_hdr = *hdr;
0091     switch (!!data * *ver) {
0092     case 0x10:
0093         p->timing_10_WR    = nvbios_rd08(bios, data + 0x00);
0094         p->timing_10_WTR   = nvbios_rd08(bios, data + 0x01);
0095         p->timing_10_CL    = nvbios_rd08(bios, data + 0x02);
0096         p->timing_10_RC    = nvbios_rd08(bios, data + 0x03);
0097         p->timing_10_RFC   = nvbios_rd08(bios, data + 0x05);
0098         p->timing_10_RAS   = nvbios_rd08(bios, data + 0x07);
0099         p->timing_10_RP    = nvbios_rd08(bios, data + 0x09);
0100         p->timing_10_RCDRD = nvbios_rd08(bios, data + 0x0a);
0101         p->timing_10_RCDWR = nvbios_rd08(bios, data + 0x0b);
0102         p->timing_10_RRD   = nvbios_rd08(bios, data + 0x0c);
0103         p->timing_10_13    = nvbios_rd08(bios, data + 0x0d);
0104         p->timing_10_ODT   = nvbios_rd08(bios, data + 0x0e) & 0x07;
0105         if (p->ramcfg_ver >= 0x10)
0106             p->ramcfg_RON = nvbios_rd08(bios, data + 0x0e) & 0x07;
0107
0108         p->timing_10_24  = 0xff;
0109         p->timing_10_21  = 0;
0110         p->timing_10_20  = 0;
0111         p->timing_10_CWL = 0;
0112         p->timing_10_18  = 0;
0113         p->timing_10_16  = 0;
0114
0115         switch (min_t(u8, *hdr, 25)) {
0116         case 25:
0117             p->timing_10_24  = nvbios_rd08(bios, data + 0x18);
0118             fallthrough;
0119         case 24:
0120         case 23:
0121         case 22:
0122             p->timing_10_21  = nvbios_rd08(bios, data + 0x15);
0123             fallthrough;
0124         case 21:
0125             p->timing_10_20  = nvbios_rd08(bios, data + 0x14);
0126             fallthrough;
0127         case 20:
0128             p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
0129             fallthrough;
0130         case 19:
0131             p->timing_10_18  = nvbios_rd08(bios, data + 0x12);
0132             fallthrough;
0133         case 18:
0134         case 17:
0135             p->timing_10_16  = nvbios_rd08(bios, data + 0x10);
0136         }
0137
0138         break;
0139     case 0x20:
0140         p->timing[0] = nvbios_rd32(bios, data + 0x00);
0141         p->timing[1] = nvbios_rd32(bios, data + 0x04);
0142         p->timing[2] = nvbios_rd32(bios, data + 0x08);
0143         p->timing[3] = nvbios_rd32(bios, data + 0x0c);
0144         p->timing[4] = nvbios_rd32(bios, data + 0x10);
0145         p->timing[5] = nvbios_rd32(bios, data + 0x14);
0146         p->timing[6] = nvbios_rd32(bios, data + 0x18);
0147         p->timing[7] = nvbios_rd32(bios, data + 0x1c);
0148         p->timing[8] = nvbios_rd32(bios, data + 0x20);
0149         p->timing[9] = nvbios_rd32(bios, data + 0x24);
0150         p->timing[10] = nvbios_rd32(bios, data + 0x28);
0151         p->timing_20_2e_03 = (nvbios_rd08(bios, data + 0x2e) & 0x03) >> 0;
0152         p->timing_20_2e_30 = (nvbios_rd08(bios, data + 0x2e) & 0x30) >> 4;
0153         p->timing_20_2e_c0 = (nvbios_rd08(bios, data + 0x2e) & 0xc0) >> 6;
0154         p->timing_20_2f_03 = (nvbios_rd08(bios, data + 0x2f) & 0x03) >> 0;
0155         temp = nvbios_rd16(bios, data + 0x2c);
0156         p->timing_20_2c_003f = (temp & 0x003f) >> 0;
0157         p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
0158         p->timing_20_30_07 = (nvbios_rd08(bios, data + 0x30) & 0x07) >> 0;
0159         p->timing_20_30_f8 = (nvbios_rd08(bios, data + 0x30) & 0xf8) >> 3;
0160         temp = nvbios_rd16(bios, data + 0x31);
0161         p->timing_20_31_0007 = (temp & 0x0007) >> 0;
0162         p->timing_20_31_0078 = (temp & 0x0078) >> 3;
0163         p->timing_20_31_0780 = (temp & 0x0780) >> 7;
0164         p->timing_20_31_0800 = (temp & 0x0800) >> 11;
0165         p->timing_20_31_7000 = (temp & 0x7000) >> 12;
0166         p->timing_20_31_8000 = (temp & 0x8000) >> 15;
0167         break;
0168     default:
0169         data = 0;
0170         break;
0171     }
0172     return data;
0173 }