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0001 /*
0002  * Copyright 2013 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include <subdev/bios.h>
0025 #include <subdev/bios/bit.h>
0026 #include <subdev/bios/rammap.h>
0027 
0028 u32
0029 nvbios_rammapTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
0030         u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
0031 {
0032     struct bit_entry bit_P;
0033     u32 rammap = 0x0000;
0034 
0035     if (!bit_entry(bios, 'P', &bit_P)) {
0036         if (bit_P.version == 2)
0037             rammap = nvbios_rd32(bios, bit_P.offset + 4);
0038 
0039         if (rammap) {
0040             *ver = nvbios_rd08(bios, rammap + 0);
0041             switch (*ver) {
0042             case 0x10:
0043             case 0x11:
0044                 *hdr = nvbios_rd08(bios, rammap + 1);
0045                 *cnt = nvbios_rd08(bios, rammap + 5);
0046                 *len = nvbios_rd08(bios, rammap + 2);
0047                 *snr = nvbios_rd08(bios, rammap + 4);
0048                 *ssz = nvbios_rd08(bios, rammap + 3);
0049                 return rammap;
0050             default:
0051                 break;
0052             }
0053         }
0054     }
0055 
0056     return 0x0000;
0057 }
0058 
0059 u32
0060 nvbios_rammapEe(struct nvkm_bios *bios, int idx,
0061         u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
0062 {
0063     u8  snr, ssz;
0064     u32 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz);
0065     if (rammap && idx < *cnt) {
0066         rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
0067         *hdr = *len;
0068         *cnt = snr;
0069         *len = ssz;
0070         return rammap;
0071     }
0072     return 0x0000;
0073 }
0074 
0075 /* Pretend a performance mode is also a rammap entry, helps coalesce entries
0076  * later on */
0077 u32
0078 nvbios_rammapEp_from_perf(struct nvkm_bios *bios, u32 data, u8 size,
0079         struct nvbios_ramcfg *p)
0080 {
0081     memset(p, 0x00, sizeof(*p));
0082 
0083     p->rammap_00_16_20 = (nvbios_rd08(bios, data + 0x16) & 0x20) >> 5;
0084     p->rammap_00_16_40 = (nvbios_rd08(bios, data + 0x16) & 0x40) >> 6;
0085     p->rammap_00_17_02 = (nvbios_rd08(bios, data + 0x17) & 0x02) >> 1;
0086 
0087     return data;
0088 }
0089 
0090 u32
0091 nvbios_rammapEp(struct nvkm_bios *bios, int idx,
0092         u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
0093 {
0094     u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp;
0095     memset(p, 0x00, sizeof(*p));
0096     p->rammap_ver = *ver;
0097     p->rammap_hdr = *hdr;
0098     switch (!!data * *ver) {
0099     case 0x10:
0100         p->rammap_min      =  nvbios_rd16(bios, data + 0x00);
0101         p->rammap_max      =  nvbios_rd16(bios, data + 0x02);
0102         p->rammap_10_04_02 = (nvbios_rd08(bios, data + 0x04) & 0x02) >> 1;
0103         p->rammap_10_04_08 = (nvbios_rd08(bios, data + 0x04) & 0x08) >> 3;
0104         break;
0105     case 0x11:
0106         p->rammap_min      =  nvbios_rd16(bios, data + 0x00);
0107         p->rammap_max      =  nvbios_rd16(bios, data + 0x02);
0108         p->rammap_11_08_01 = (nvbios_rd08(bios, data + 0x08) & 0x01) >> 0;
0109         p->rammap_11_08_0c = (nvbios_rd08(bios, data + 0x08) & 0x0c) >> 2;
0110         p->rammap_11_08_10 = (nvbios_rd08(bios, data + 0x08) & 0x10) >> 4;
0111         temp = nvbios_rd32(bios, data + 0x09);
0112         p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0;
0113         p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9;
0114         p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18;
0115         p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19;
0116         p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20;
0117         p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25;
0118         p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26;
0119         p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27;
0120         p->rammap_11_0d    =  nvbios_rd08(bios, data + 0x0d);
0121         p->rammap_11_0e    =  nvbios_rd08(bios, data + 0x0e);
0122         p->rammap_11_0f    =  nvbios_rd08(bios, data + 0x0f);
0123         p->rammap_11_11_0c = (nvbios_rd08(bios, data + 0x11) & 0x0c) >> 2;
0124         break;
0125     default:
0126         data = 0;
0127         break;
0128     }
0129     return data;
0130 }
0131 
0132 u32
0133 nvbios_rammapEm(struct nvkm_bios *bios, u16 mhz,
0134         u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *info)
0135 {
0136     int idx = 0;
0137     u32 data;
0138     while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) {
0139         if (mhz >= info->rammap_min && mhz <= info->rammap_max)
0140             break;
0141     }
0142     return data;
0143 }
0144 
0145 u32
0146 nvbios_rammapSe(struct nvkm_bios *bios, u32 data,
0147         u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr)
0148 {
0149     if (idx < ecnt) {
0150         data = data + ehdr + (idx * elen);
0151         *ver = ever;
0152         *hdr = elen;
0153         return data;
0154     }
0155     return 0;
0156 }
0157 
0158 u32
0159 nvbios_rammapSp_from_perf(struct nvkm_bios *bios, u32 data, u8 size, int idx,
0160         struct nvbios_ramcfg *p)
0161 {
0162     data += (idx * size);
0163 
0164     if (size < 11)
0165         return 0x00000000;
0166 
0167     p->ramcfg_ver = 0;
0168     p->ramcfg_timing   =  nvbios_rd08(bios, data + 0x01);
0169     p->ramcfg_00_03_01 = (nvbios_rd08(bios, data + 0x03) & 0x01) >> 0;
0170     p->ramcfg_00_03_02 = (nvbios_rd08(bios, data + 0x03) & 0x02) >> 1;
0171     p->ramcfg_DLLoff   = (nvbios_rd08(bios, data + 0x03) & 0x04) >> 2;
0172     p->ramcfg_00_03_08 = (nvbios_rd08(bios, data + 0x03) & 0x08) >> 3;
0173     p->ramcfg_RON      = (nvbios_rd08(bios, data + 0x03) & 0x10) >> 3;
0174     p->ramcfg_FBVDDQ   = (nvbios_rd08(bios, data + 0x03) & 0x80) >> 7;
0175     p->ramcfg_00_04_02 = (nvbios_rd08(bios, data + 0x04) & 0x02) >> 1;
0176     p->ramcfg_00_04_04 = (nvbios_rd08(bios, data + 0x04) & 0x04) >> 2;
0177     p->ramcfg_00_04_20 = (nvbios_rd08(bios, data + 0x04) & 0x20) >> 5;
0178     p->ramcfg_00_05    = (nvbios_rd08(bios, data + 0x05) & 0xff) >> 0;
0179     p->ramcfg_00_06    = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0;
0180     p->ramcfg_00_07    = (nvbios_rd08(bios, data + 0x07) & 0xff) >> 0;
0181     p->ramcfg_00_08    = (nvbios_rd08(bios, data + 0x08) & 0xff) >> 0;
0182     p->ramcfg_00_09    = (nvbios_rd08(bios, data + 0x09) & 0xff) >> 0;
0183     p->ramcfg_00_0a_0f = (nvbios_rd08(bios, data + 0x0a) & 0x0f) >> 0;
0184     p->ramcfg_00_0a_f0 = (nvbios_rd08(bios, data + 0x0a) & 0xf0) >> 4;
0185 
0186     return data;
0187 }
0188 
0189 u32
0190 nvbios_rammapSp(struct nvkm_bios *bios, u32 data,
0191         u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
0192         u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
0193 {
0194     data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
0195     p->ramcfg_ver = *ver;
0196     p->ramcfg_hdr = *hdr;
0197     switch (!!data * *ver) {
0198     case 0x10:
0199         p->ramcfg_timing   =  nvbios_rd08(bios, data + 0x01);
0200         p->ramcfg_10_02_01 = (nvbios_rd08(bios, data + 0x02) & 0x01) >> 0;
0201         p->ramcfg_10_02_02 = (nvbios_rd08(bios, data + 0x02) & 0x02) >> 1;
0202         p->ramcfg_10_02_04 = (nvbios_rd08(bios, data + 0x02) & 0x04) >> 2;
0203         p->ramcfg_10_02_08 = (nvbios_rd08(bios, data + 0x02) & 0x08) >> 3;
0204         p->ramcfg_10_02_10 = (nvbios_rd08(bios, data + 0x02) & 0x10) >> 4;
0205         p->ramcfg_10_02_20 = (nvbios_rd08(bios, data + 0x02) & 0x20) >> 5;
0206         p->ramcfg_DLLoff   = (nvbios_rd08(bios, data + 0x02) & 0x40) >> 6;
0207         p->ramcfg_10_03_0f = (nvbios_rd08(bios, data + 0x03) & 0x0f) >> 0;
0208         p->ramcfg_10_04_01 = (nvbios_rd08(bios, data + 0x04) & 0x01) >> 0;
0209         p->ramcfg_FBVDDQ   = (nvbios_rd08(bios, data + 0x04) & 0x08) >> 3;
0210         p->ramcfg_10_05    = (nvbios_rd08(bios, data + 0x05) & 0xff) >> 0;
0211         p->ramcfg_10_06    = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0;
0212         p->ramcfg_10_07    = (nvbios_rd08(bios, data + 0x07) & 0xff) >> 0;
0213         p->ramcfg_10_08    = (nvbios_rd08(bios, data + 0x08) & 0xff) >> 0;
0214         p->ramcfg_10_09_0f = (nvbios_rd08(bios, data + 0x09) & 0x0f) >> 0;
0215         p->ramcfg_10_09_f0 = (nvbios_rd08(bios, data + 0x09) & 0xf0) >> 4;
0216         break;
0217     case 0x11:
0218         p->ramcfg_timing   =  nvbios_rd08(bios, data + 0x00);
0219         p->ramcfg_11_01_01 = (nvbios_rd08(bios, data + 0x01) & 0x01) >> 0;
0220         p->ramcfg_11_01_02 = (nvbios_rd08(bios, data + 0x01) & 0x02) >> 1;
0221         p->ramcfg_11_01_04 = (nvbios_rd08(bios, data + 0x01) & 0x04) >> 2;
0222         p->ramcfg_11_01_08 = (nvbios_rd08(bios, data + 0x01) & 0x08) >> 3;
0223         p->ramcfg_11_01_10 = (nvbios_rd08(bios, data + 0x01) & 0x10) >> 4;
0224         p->ramcfg_DLLoff =   (nvbios_rd08(bios, data + 0x01) & 0x20) >> 5;
0225         p->ramcfg_11_01_40 = (nvbios_rd08(bios, data + 0x01) & 0x40) >> 6;
0226         p->ramcfg_11_01_80 = (nvbios_rd08(bios, data + 0x01) & 0x80) >> 7;
0227         p->ramcfg_11_02_03 = (nvbios_rd08(bios, data + 0x02) & 0x03) >> 0;
0228         p->ramcfg_11_02_04 = (nvbios_rd08(bios, data + 0x02) & 0x04) >> 2;
0229         p->ramcfg_11_02_08 = (nvbios_rd08(bios, data + 0x02) & 0x08) >> 3;
0230         p->ramcfg_11_02_10 = (nvbios_rd08(bios, data + 0x02) & 0x10) >> 4;
0231         p->ramcfg_11_02_40 = (nvbios_rd08(bios, data + 0x02) & 0x40) >> 6;
0232         p->ramcfg_11_02_80 = (nvbios_rd08(bios, data + 0x02) & 0x80) >> 7;
0233         p->ramcfg_11_03_0f = (nvbios_rd08(bios, data + 0x03) & 0x0f) >> 0;
0234         p->ramcfg_11_03_30 = (nvbios_rd08(bios, data + 0x03) & 0x30) >> 4;
0235         p->ramcfg_11_03_c0 = (nvbios_rd08(bios, data + 0x03) & 0xc0) >> 6;
0236         p->ramcfg_11_03_f0 = (nvbios_rd08(bios, data + 0x03) & 0xf0) >> 4;
0237         p->ramcfg_11_04    = (nvbios_rd08(bios, data + 0x04) & 0xff) >> 0;
0238         p->ramcfg_11_06    = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0;
0239         p->ramcfg_11_07_02 = (nvbios_rd08(bios, data + 0x07) & 0x02) >> 1;
0240         p->ramcfg_11_07_04 = (nvbios_rd08(bios, data + 0x07) & 0x04) >> 2;
0241         p->ramcfg_11_07_08 = (nvbios_rd08(bios, data + 0x07) & 0x08) >> 3;
0242         p->ramcfg_11_07_10 = (nvbios_rd08(bios, data + 0x07) & 0x10) >> 4;
0243         p->ramcfg_11_07_40 = (nvbios_rd08(bios, data + 0x07) & 0x40) >> 6;
0244         p->ramcfg_11_07_80 = (nvbios_rd08(bios, data + 0x07) & 0x80) >> 7;
0245         p->ramcfg_11_08_01 = (nvbios_rd08(bios, data + 0x08) & 0x01) >> 0;
0246         p->ramcfg_11_08_02 = (nvbios_rd08(bios, data + 0x08) & 0x02) >> 1;
0247         p->ramcfg_11_08_04 = (nvbios_rd08(bios, data + 0x08) & 0x04) >> 2;
0248         p->ramcfg_11_08_08 = (nvbios_rd08(bios, data + 0x08) & 0x08) >> 3;
0249         p->ramcfg_11_08_10 = (nvbios_rd08(bios, data + 0x08) & 0x10) >> 4;
0250         p->ramcfg_11_08_20 = (nvbios_rd08(bios, data + 0x08) & 0x20) >> 5;
0251         p->ramcfg_11_09    = (nvbios_rd08(bios, data + 0x09) & 0xff) >> 0;
0252         break;
0253     default:
0254         data = 0;
0255         break;
0256     }
0257     return data;
0258 }
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