0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022 #include "gf100.h"
0023
0024 #include <core/memory.h>
0025 #include <subdev/timer.h>
0026
0027 static void
0028 tu102_bar_bar2_wait(struct nvkm_bar *bar)
0029 {
0030 struct nvkm_device *device = bar->subdev.device;
0031 nvkm_msec(device, 2000,
0032 if (!(nvkm_rd32(device, 0xb80f50) & 0x0000000c))
0033 break;
0034 );
0035 }
0036
0037 static void
0038 tu102_bar_bar2_fini(struct nvkm_bar *bar)
0039 {
0040 nvkm_mask(bar->subdev.device, 0xb80f48, 0x80000000, 0x00000000);
0041 }
0042
0043 static void
0044 tu102_bar_bar2_init(struct nvkm_bar *base)
0045 {
0046 struct nvkm_device *device = base->subdev.device;
0047 struct gf100_bar *bar = gf100_bar(base);
0048 u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12;
0049 if (bar->bar2_halve)
0050 addr |= 0x40000000;
0051 nvkm_wr32(device, 0xb80f48, 0x80000000 | addr);
0052 }
0053
0054 static void
0055 tu102_bar_bar1_wait(struct nvkm_bar *bar)
0056 {
0057 struct nvkm_device *device = bar->subdev.device;
0058 nvkm_msec(device, 2000,
0059 if (!(nvkm_rd32(device, 0xb80f50) & 0x00000003))
0060 break;
0061 );
0062 }
0063
0064 static void
0065 tu102_bar_bar1_fini(struct nvkm_bar *bar)
0066 {
0067 nvkm_mask(bar->subdev.device, 0xb80f40, 0x80000000, 0x00000000);
0068 }
0069
0070 static void
0071 tu102_bar_bar1_init(struct nvkm_bar *base)
0072 {
0073 struct nvkm_device *device = base->subdev.device;
0074 struct gf100_bar *bar = gf100_bar(base);
0075 const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12;
0076 nvkm_wr32(device, 0xb80f40, 0x80000000 | addr);
0077 }
0078
0079 static const struct nvkm_bar_func
0080 tu102_bar = {
0081 .dtor = gf100_bar_dtor,
0082 .oneinit = gf100_bar_oneinit,
0083 .bar1.init = tu102_bar_bar1_init,
0084 .bar1.fini = tu102_bar_bar1_fini,
0085 .bar1.wait = tu102_bar_bar1_wait,
0086 .bar1.vmm = gf100_bar_bar1_vmm,
0087 .bar2.init = tu102_bar_bar2_init,
0088 .bar2.fini = tu102_bar_bar2_fini,
0089 .bar2.wait = tu102_bar_bar2_wait,
0090 .bar2.vmm = gf100_bar_bar2_vmm,
0091 .flush = g84_bar_flush,
0092 };
0093
0094 int
0095 tu102_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0096 struct nvkm_bar **pbar)
0097 {
0098 return gf100_bar_new_(&tu102_bar, device, type, inst, pbar);
0099 }