subdev/bar/nv50.c

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include "nv50.h"
0025
0026 #include <core/gpuobj.h>
0027 #include <subdev/fb.h>
0028 #include <subdev/mmu.h>
0029 #include <subdev/timer.h>
0030
0031 static void
0032 nv50_bar_flush(struct nvkm_bar *base)
0033 {
0034     struct nv50_bar *bar = nv50_bar(base);
0035     struct nvkm_device *device = bar->base.subdev.device;
0036     unsigned long flags;
0037     spin_lock_irqsave(&bar->base.lock, flags);
0038     nvkm_wr32(device, 0x00330c, 0x00000001);
0039     nvkm_msec(device, 2000,
0040         if (!(nvkm_rd32(device, 0x00330c) & 0x00000002))
0041             break;
0042     );
0043     spin_unlock_irqrestore(&bar->base.lock, flags);
0044 }
0045
0046 struct nvkm_vmm *
0047 nv50_bar_bar1_vmm(struct nvkm_bar *base)
0048 {
0049     return nv50_bar(base)->bar1_vmm;
0050 }
0051
0052 void
0053 nv50_bar_bar1_wait(struct nvkm_bar *base)
0054 {
0055     nvkm_bar_flush(base);
0056 }
0057
0058 void
0059 nv50_bar_bar1_fini(struct nvkm_bar *bar)
0060 {
0061     nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000);
0062 }
0063
0064 void
0065 nv50_bar_bar1_init(struct nvkm_bar *base)
0066 {
0067     struct nvkm_device *device = base->subdev.device;
0068     struct nv50_bar *bar = nv50_bar(base);
0069     nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
0070 }
0071
0072 struct nvkm_vmm *
0073 nv50_bar_bar2_vmm(struct nvkm_bar *base)
0074 {
0075     return nv50_bar(base)->bar2_vmm;
0076 }
0077
0078 void
0079 nv50_bar_bar2_fini(struct nvkm_bar *bar)
0080 {
0081     nvkm_wr32(bar->subdev.device, 0x00170c, 0x00000000);
0082 }
0083
0084 void
0085 nv50_bar_bar2_init(struct nvkm_bar *base)
0086 {
0087     struct nvkm_device *device = base->subdev.device;
0088     struct nv50_bar *bar = nv50_bar(base);
0089     nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);
0090     nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);
0091     nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4);
0092 }
0093
0094 void
0095 nv50_bar_init(struct nvkm_bar *base)
0096 {
0097     struct nv50_bar *bar = nv50_bar(base);
0098     struct nvkm_device *device = bar->base.subdev.device;
0099     int i;
0100
0101     for (i = 0; i < 8; i++)
0102         nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);
0103 }
0104
0105 int
0106 nv50_bar_oneinit(struct nvkm_bar *base)
0107 {
0108     struct nv50_bar *bar = nv50_bar(base);
0109     struct nvkm_device *device = bar->base.subdev.device;
0110     static struct lock_class_key bar1_lock;
0111     static struct lock_class_key bar2_lock;
0112     u64 start, limit, size;
0113     int ret;
0114
0115     ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
0116     if (ret)
0117         return ret;
0118
0119     ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem,
0120                   &bar->pad);
0121     if (ret)
0122         return ret;
0123
0124     ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);
0125     if (ret)
0126         return ret;
0127
0128     /* BAR2 */
0129     start = 0x0100000000ULL;
0130     size = device->func->resource_size(device, 3);
0131     if (!size)
0132         return -ENOMEM;
0133     limit = start + size;
0134
0135     ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0,
0136                &bar2_lock, "bar2", &bar->bar2_vmm);
0137     if (ret)
0138         return ret;
0139
0140     atomic_inc(&bar->bar2_vmm->engref[NVKM_SUBDEV_BAR]);
0141     bar->bar2_vmm->debug = bar->base.subdev.debug;
0142
0143     ret = nvkm_vmm_boot(bar->bar2_vmm);
0144     if (ret)
0145         return ret;
0146
0147     ret = nvkm_vmm_join(bar->bar2_vmm, bar->mem->memory);
0148     if (ret)
0149         return ret;
0150
0151     ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2);
0152     if (ret)
0153         return ret;
0154
0155     nvkm_kmap(bar->bar2);
0156     nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);
0157     nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));
0158     nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));
0159     nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |
0160                    upper_32_bits(start));
0161     nvkm_wo32(bar->bar2, 0x10, 0x00000000);
0162     nvkm_wo32(bar->bar2, 0x14, 0x00000000);
0163     nvkm_done(bar->bar2);
0164
0165     bar->base.subdev.oneinit = true;
0166     nvkm_bar_bar2_init(device);
0167
0168     /* BAR1 */
0169     start = 0x0000000000ULL;
0170     size = device->func->resource_size(device, 1);
0171     if (!size)
0172         return -ENOMEM;
0173     limit = start + size;
0174
0175     ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0,
0176                &bar1_lock, "bar1", &bar->bar1_vmm);
0177     if (ret)
0178         return ret;
0179
0180     atomic_inc(&bar->bar1_vmm->engref[NVKM_SUBDEV_BAR]);
0181     bar->bar1_vmm->debug = bar->base.subdev.debug;
0182
0183     ret = nvkm_vmm_join(bar->bar1_vmm, bar->mem->memory);
0184     if (ret)
0185         return ret;
0186
0187     ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);
0188     if (ret)
0189         return ret;
0190
0191     nvkm_kmap(bar->bar1);
0192     nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
0193     nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
0194     nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
0195     nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
0196                    upper_32_bits(start));
0197     nvkm_wo32(bar->bar1, 0x10, 0x00000000);
0198     nvkm_wo32(bar->bar1, 0x14, 0x00000000);
0199     nvkm_done(bar->bar1);
0200     return 0;
0201 }
0202
0203 void *
0204 nv50_bar_dtor(struct nvkm_bar *base)
0205 {
0206     struct nv50_bar *bar = nv50_bar(base);
0207     if (bar->mem) {
0208         nvkm_gpuobj_del(&bar->bar1);
0209         nvkm_vmm_part(bar->bar1_vmm, bar->mem->memory);
0210         nvkm_vmm_unref(&bar->bar1_vmm);
0211         nvkm_gpuobj_del(&bar->bar2);
0212         nvkm_vmm_part(bar->bar2_vmm, bar->mem->memory);
0213         nvkm_vmm_unref(&bar->bar2_vmm);
0214         nvkm_gpuobj_del(&bar->pgd);
0215         nvkm_gpuobj_del(&bar->pad);
0216         nvkm_gpuobj_del(&bar->mem);
0217     }
0218     return bar;
0219 }
0220
0221 int
0222 nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device,
0223           enum nvkm_subdev_type type, int inst, u32 pgd_addr, struct nvkm_bar **pbar)
0224 {
0225     struct nv50_bar *bar;
0226     if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
0227         return -ENOMEM;
0228     nvkm_bar_ctor(func, device, type, inst, &bar->base);
0229     bar->pgd_addr = pgd_addr;
0230     *pbar = &bar->base;
0231     return 0;
0232 }
0233
0234 static const struct nvkm_bar_func
0235 nv50_bar_func = {
0236     .dtor = nv50_bar_dtor,
0237     .oneinit = nv50_bar_oneinit,
0238     .init = nv50_bar_init,
0239     .bar1.init = nv50_bar_bar1_init,
0240     .bar1.fini = nv50_bar_bar1_fini,
0241     .bar1.wait = nv50_bar_bar1_wait,
0242     .bar1.vmm = nv50_bar_bar1_vmm,
0243     .bar2.init = nv50_bar_bar2_init,
0244     .bar2.fini = nv50_bar_bar2_fini,
0245     .bar2.wait = nv50_bar_bar1_wait,
0246     .bar2.vmm = nv50_bar_bar2_vmm,
0247     .flush = nv50_bar_flush,
0248 };
0249
0250 int
0251 nv50_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0252          struct nvkm_bar **pbar)
0253 {
0254     return nv50_bar_new_(&nv50_bar_func, device, type, inst, 0x1400, pbar);
0255 }