nvkm/nvfw/flcn.c

0001 /*
0002  * Copyright 2019 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #include <core/subdev.h>
0023 #include <nvfw/flcn.h>
0024
0025 void
0026 loader_config_dump(struct nvkm_subdev *subdev, const struct loader_config *hdr)
0027 {
0028     nvkm_debug(subdev, "loaderConfig\n");
0029     nvkm_debug(subdev, "\tdmaIdx        : %d\n", hdr->dma_idx);
0030     nvkm_debug(subdev, "\tcodeDmaBase   : 0x%xx\n", hdr->code_dma_base);
0031     nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
0032     nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
0033     nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
0034     nvkm_debug(subdev, "\tdataDmaBase   : 0x%x\n", hdr->data_dma_base);
0035     nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
0036     nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
0037     nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
0038     nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
0039     nvkm_debug(subdev, "\tcodeDmaBase1  : 0x%x\n", hdr->code_dma_base1);
0040     nvkm_debug(subdev, "\tdataDmaBase1  : 0x%x\n", hdr->data_dma_base1);
0041     nvkm_debug(subdev, "\tovlyDmaBase1  : 0x%x\n", hdr->overlay_dma_base1);
0042 }
0043
0044 void
0045 loader_config_v1_dump(struct nvkm_subdev *subdev,
0046               const struct loader_config_v1 *hdr)
0047 {
0048     nvkm_debug(subdev, "loaderConfig\n");
0049     nvkm_debug(subdev, "\treserved      : 0x%08x\n", hdr->reserved);
0050     nvkm_debug(subdev, "\tdmaIdx        : %d\n", hdr->dma_idx);
0051     nvkm_debug(subdev, "\tcodeDmaBase   : 0x%llxx\n", hdr->code_dma_base);
0052     nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
0053     nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
0054     nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
0055     nvkm_debug(subdev, "\tdataDmaBase   : 0x%llx\n", hdr->data_dma_base);
0056     nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
0057     nvkm_debug(subdev, "\toverlayDmaBase: 0x%llx\n", hdr->overlay_dma_base);
0058     nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
0059     nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
0060 }
0061
0062 void
0063 flcn_bl_dmem_desc_dump(struct nvkm_subdev *subdev,
0064                const struct flcn_bl_dmem_desc *hdr)
0065 {
0066     nvkm_debug(subdev, "flcnBlDmemDesc\n");
0067     nvkm_debug(subdev, "\treserved      : 0x%08x 0x%08x 0x%08x 0x%08x\n",
0068            hdr->reserved[0], hdr->reserved[1], hdr->reserved[2],
0069            hdr->reserved[3]);
0070     nvkm_debug(subdev, "\tsignature     : 0x%08x 0x%08x 0x%08x 0x%08x\n",
0071            hdr->signature[0], hdr->signature[1], hdr->signature[2],
0072            hdr->signature[3]);
0073     nvkm_debug(subdev, "\tctxDma        : %d\n", hdr->ctx_dma);
0074     nvkm_debug(subdev, "\tcodeDmaBase   : 0x%x\n", hdr->code_dma_base);
0075     nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
0076     nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
0077     nvkm_debug(subdev, "\tsecCodeOff    : 0x%x\n", hdr->sec_code_off);
0078     nvkm_debug(subdev, "\tsecCodeSize   : 0x%x\n", hdr->sec_code_size);
0079     nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
0080     nvkm_debug(subdev, "\tdataDmaBase   : 0x%x\n", hdr->data_dma_base);
0081     nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
0082     nvkm_debug(subdev, "\tcodeDmaBase1  : 0x%x\n", hdr->code_dma_base1);
0083     nvkm_debug(subdev, "\tdataDmaBase1  : 0x%x\n", hdr->data_dma_base1);
0084 }
0085
0086 void
0087 flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *subdev,
0088               const struct flcn_bl_dmem_desc_v1 *hdr)
0089 {
0090     nvkm_debug(subdev, "flcnBlDmemDesc\n");
0091     nvkm_debug(subdev, "\treserved      : 0x%08x 0x%08x 0x%08x 0x%08x\n",
0092            hdr->reserved[0], hdr->reserved[1], hdr->reserved[2],
0093            hdr->reserved[3]);
0094     nvkm_debug(subdev, "\tsignature     : 0x%08x 0x%08x 0x%08x 0x%08x\n",
0095            hdr->signature[0], hdr->signature[1], hdr->signature[2],
0096            hdr->signature[3]);
0097     nvkm_debug(subdev, "\tctxDma        : %d\n", hdr->ctx_dma);
0098     nvkm_debug(subdev, "\tcodeDmaBase   : 0x%llx\n", hdr->code_dma_base);
0099     nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
0100     nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
0101     nvkm_debug(subdev, "\tsecCodeOff    : 0x%x\n", hdr->sec_code_off);
0102     nvkm_debug(subdev, "\tsecCodeSize   : 0x%x\n", hdr->sec_code_size);
0103     nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
0104     nvkm_debug(subdev, "\tdataDmaBase   : 0x%llx\n", hdr->data_dma_base);
0105     nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
0106 }
0107
0108 void
0109 flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *subdev,
0110               const struct flcn_bl_dmem_desc_v2 *hdr)
0111 {
0112     flcn_bl_dmem_desc_v1_dump(subdev, (void *)hdr);
0113     nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
0114     nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
0115 }