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0001 /*
0002  * Copyright 2019 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #include <core/subdev.h>
0023 #include <nvfw/acr.h>
0024 
0025 void
0026 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr)
0027 {
0028     nvkm_debug(subdev, "wprHeader\n");
0029     nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
0030     nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
0031     nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
0032     nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
0033     nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
0034 }
0035 
0036 void
0037 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr)
0038 {
0039     nvkm_debug(subdev, "wprHeader\n");
0040     nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
0041     nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
0042     nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
0043     nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
0044     nvkm_debug(subdev, "\tbinVersion    : %d\n", hdr->bin_version);
0045     nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
0046 }
0047 
0048 static void
0049 lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr)
0050 {
0051     nvkm_debug(subdev, "lsbHeader\n");
0052     nvkm_debug(subdev, "\tucodeOff      : 0x%x\n", hdr->ucode_off);
0053     nvkm_debug(subdev, "\tucodeSize     : 0x%x\n", hdr->ucode_size);
0054     nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
0055     nvkm_debug(subdev, "\tblCodeSize    : 0x%x\n", hdr->bl_code_size);
0056     nvkm_debug(subdev, "\tblImemOff     : 0x%x\n", hdr->bl_imem_off);
0057     nvkm_debug(subdev, "\tblDataOff     : 0x%x\n", hdr->bl_data_off);
0058     nvkm_debug(subdev, "\tblDataSize    : 0x%x\n", hdr->bl_data_size);
0059     nvkm_debug(subdev, "\tappCodeOff    : 0x%x\n", hdr->app_code_off);
0060     nvkm_debug(subdev, "\tappCodeSize   : 0x%x\n", hdr->app_code_size);
0061     nvkm_debug(subdev, "\tappDataOff    : 0x%x\n", hdr->app_data_off);
0062     nvkm_debug(subdev, "\tappDataSize   : 0x%x\n", hdr->app_data_size);
0063     nvkm_debug(subdev, "\tflags         : 0x%x\n", hdr->flags);
0064 }
0065 
0066 void
0067 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr)
0068 {
0069     lsb_header_tail_dump(subdev, &hdr->tail);
0070 }
0071 
0072 void
0073 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr)
0074 {
0075     lsb_header_tail_dump(subdev, &hdr->tail);
0076 }
0077 
0078 void
0079 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr)
0080 {
0081     int i;
0082 
0083     nvkm_debug(subdev, "acrDesc\n");
0084     nvkm_debug(subdev, "\twprRegionId  : %d\n", hdr->wpr_region_id);
0085     nvkm_debug(subdev, "\twprOffset    : 0x%x\n", hdr->wpr_offset);
0086     nvkm_debug(subdev, "\tmmuMemRange  : 0x%x\n",
0087            hdr->mmu_mem_range);
0088     nvkm_debug(subdev, "\tnoRegions    : %d\n",
0089            hdr->regions.no_regions);
0090 
0091     for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
0092         nvkm_debug(subdev, "\tregion[%d]    :\n", i);
0093         nvkm_debug(subdev, "\t  startAddr  : 0x%x\n",
0094                hdr->regions.region_props[i].start_addr);
0095         nvkm_debug(subdev, "\t  endAddr    : 0x%x\n",
0096                hdr->regions.region_props[i].end_addr);
0097         nvkm_debug(subdev, "\t  regionId   : %d\n",
0098                hdr->regions.region_props[i].region_id);
0099         nvkm_debug(subdev, "\t  readMask   : 0x%x\n",
0100                hdr->regions.region_props[i].read_mask);
0101         nvkm_debug(subdev, "\t  writeMask  : 0x%x\n",
0102                hdr->regions.region_props[i].write_mask);
0103         nvkm_debug(subdev, "\t  clientMask : 0x%x\n",
0104                hdr->regions.region_props[i].client_mask);
0105     }
0106 
0107     nvkm_debug(subdev, "\tucodeBlobSize: %d\n",
0108            hdr->ucode_blob_size);
0109     nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n",
0110            hdr->ucode_blob_base);
0111     nvkm_debug(subdev, "\tvprEnabled   : %d\n",
0112            hdr->vpr_desc.vpr_enabled);
0113     nvkm_debug(subdev, "\tvprStart     : 0x%x\n",
0114            hdr->vpr_desc.vpr_start);
0115     nvkm_debug(subdev, "\tvprEnd       : 0x%x\n",
0116            hdr->vpr_desc.vpr_end);
0117     nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",
0118            hdr->vpr_desc.hdcp_policies);
0119 }
0120 
0121 void
0122 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr)
0123 {
0124     int i;
0125 
0126     nvkm_debug(subdev, "acrDesc\n");
0127     nvkm_debug(subdev, "\twprRegionId         : %d\n", hdr->wpr_region_id);
0128     nvkm_debug(subdev, "\twprOffset           : 0x%x\n", hdr->wpr_offset);
0129     nvkm_debug(subdev, "\tmmuMemoryRange      : 0x%x\n",
0130            hdr->mmu_memory_range);
0131     nvkm_debug(subdev, "\tnoRegions           : %d\n",
0132            hdr->regions.no_regions);
0133 
0134     for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
0135         nvkm_debug(subdev, "\tregion[%d]           :\n", i);
0136         nvkm_debug(subdev, "\t  startAddr         : 0x%x\n",
0137                hdr->regions.region_props[i].start_addr);
0138         nvkm_debug(subdev, "\t  endAddr           : 0x%x\n",
0139                hdr->regions.region_props[i].end_addr);
0140         nvkm_debug(subdev, "\t  regionId          : %d\n",
0141                hdr->regions.region_props[i].region_id);
0142         nvkm_debug(subdev, "\t  readMask          : 0x%x\n",
0143                hdr->regions.region_props[i].read_mask);
0144         nvkm_debug(subdev, "\t  writeMask         : 0x%x\n",
0145                hdr->regions.region_props[i].write_mask);
0146         nvkm_debug(subdev, "\t  clientMask        : 0x%x\n",
0147                hdr->regions.region_props[i].client_mask);
0148         nvkm_debug(subdev, "\t  shadowMemStartAddr: 0x%x\n",
0149                hdr->regions.region_props[i].shadow_mem_start_addr);
0150     }
0151 
0152     nvkm_debug(subdev, "\tucodeBlobSize       : %d\n",
0153            hdr->ucode_blob_size);
0154     nvkm_debug(subdev, "\tucodeBlobBase       : 0x%llx\n",
0155            hdr->ucode_blob_base);
0156     nvkm_debug(subdev, "\tvprEnabled          : %d\n",
0157            hdr->vpr_desc.vpr_enabled);
0158     nvkm_debug(subdev, "\tvprStart            : 0x%x\n",
0159            hdr->vpr_desc.vpr_start);
0160     nvkm_debug(subdev, "\tvprEnd              : 0x%x\n",
0161            hdr->vpr_desc.vpr_end);
0162     nvkm_debug(subdev, "\thdcpPolicies        : 0x%x\n",
0163            hdr->vpr_desc.hdcp_policies);
0164 }
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