engine/cipher/g84.c

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include <engine/cipher.h>
0025 #include <engine/fifo.h>
0026
0027 #include <core/client.h>
0028 #include <core/enum.h>
0029 #include <core/gpuobj.h>
0030
0031 #include <nvif/class.h>
0032
0033 static int
0034 g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
0035                int align, struct nvkm_gpuobj **pgpuobj)
0036 {
0037     int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
0038                   align, false, parent, pgpuobj);
0039     if (ret == 0) {
0040         nvkm_kmap(*pgpuobj);
0041         nvkm_wo32(*pgpuobj, 0x00, object->oclass);
0042         nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
0043         nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
0044         nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
0045         nvkm_done(*pgpuobj);
0046     }
0047     return ret;
0048 }
0049
0050 static const struct nvkm_object_func
0051 g84_cipher_oclass_func = {
0052     .bind = g84_cipher_oclass_bind,
0053 };
0054
0055 static int
0056 g84_cipher_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
0057                int align, struct nvkm_gpuobj **pgpuobj)
0058 {
0059     return nvkm_gpuobj_new(object->engine->subdev.device, 256,
0060                    align, true, parent, pgpuobj);
0061
0062 }
0063
0064 static const struct nvkm_object_func
0065 g84_cipher_cclass = {
0066     .bind = g84_cipher_cclass_bind,
0067 };
0068
0069 static const struct nvkm_bitfield
0070 g84_cipher_intr_mask[] = {
0071     { 0x00000001, "INVALID_STATE" },
0072     { 0x00000002, "ILLEGAL_MTHD" },
0073     { 0x00000004, "ILLEGAL_CLASS" },
0074     { 0x00000080, "QUERY" },
0075     { 0x00000100, "FAULT" },
0076     {}
0077 };
0078
0079 static void
0080 g84_cipher_intr(struct nvkm_engine *cipher)
0081 {
0082     struct nvkm_subdev *subdev = &cipher->subdev;
0083     struct nvkm_device *device = subdev->device;
0084     struct nvkm_fifo *fifo = device->fifo;
0085     struct nvkm_fifo_chan *chan;
0086     u32 stat = nvkm_rd32(device, 0x102130);
0087     u32 mthd = nvkm_rd32(device, 0x102190);
0088     u32 data = nvkm_rd32(device, 0x102194);
0089     u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff;
0090     unsigned long flags;
0091     char msg[128];
0092
0093     chan = nvkm_fifo_chan_inst(fifo, (u64)inst << 12, &flags);
0094     if (stat) {
0095         nvkm_snprintbf(msg, sizeof(msg), g84_cipher_intr_mask, stat);
0096         nvkm_error(subdev,  "%08x [%s] ch %d [%010llx %s] "
0097                     "mthd %04x data %08x\n", stat, msg,
0098                chan ? chan->chid : -1, (u64)inst << 12,
0099                chan ? chan->object.client->name : "unknown",
0100                mthd, data);
0101     }
0102     nvkm_fifo_chan_put(fifo, flags, &chan);
0103
0104     nvkm_wr32(device, 0x102130, stat);
0105     nvkm_wr32(device, 0x10200c, 0x10);
0106 }
0107
0108 static int
0109 g84_cipher_init(struct nvkm_engine *cipher)
0110 {
0111     struct nvkm_device *device = cipher->subdev.device;
0112     nvkm_wr32(device, 0x102130, 0xffffffff);
0113     nvkm_wr32(device, 0x102140, 0xffffffbf);
0114     nvkm_wr32(device, 0x10200c, 0x00000010);
0115     return 0;
0116 }
0117
0118 static const struct nvkm_engine_func
0119 g84_cipher = {
0120     .init = g84_cipher_init,
0121     .intr = g84_cipher_intr,
0122     .cclass = &g84_cipher_cclass,
0123     .sclass = {
0124         { -1, -1, NV74_CIPHER, &g84_cipher_oclass_func },
0125         {}
0126     }
0127 };
0128
0129 int
0130 g84_cipher_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0131            struct nvkm_engine **pengine)
0132 {
0133     return nvkm_engine_new_(&g84_cipher, device, type, inst, true, pengine);
0134 }