drm/nouveau/nouveau_chan.c

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include <nvif/push006c.h>
0025
0026 #include <nvif/class.h>
0027 #include <nvif/cl0002.h>
0028 #include <nvif/cl006b.h>
0029 #include <nvif/cl506f.h>
0030 #include <nvif/cl906f.h>
0031 #include <nvif/cla06f.h>
0032 #include <nvif/clc36f.h>
0033 #include <nvif/ioctl.h>
0034
0035 #include "nouveau_drv.h"
0036 #include "nouveau_dma.h"
0037 #include "nouveau_bo.h"
0038 #include "nouveau_chan.h"
0039 #include "nouveau_fence.h"
0040 #include "nouveau_abi16.h"
0041 #include "nouveau_vmm.h"
0042 #include "nouveau_svm.h"
0043
0044 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
0045 int nouveau_vram_pushbuf;
0046 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
0047
0048 static int
0049 nouveau_channel_killed(struct nvif_notify *ntfy)
0050 {
0051     struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill);
0052     struct nouveau_cli *cli = (void *)chan->user.client;
0053     NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
0054     atomic_set(&chan->killed, 1);
0055     if (chan->fence)
0056         nouveau_fence_context_kill(chan->fence, -ENODEV);
0057     return NVIF_NOTIFY_DROP;
0058 }
0059
0060 int
0061 nouveau_channel_idle(struct nouveau_channel *chan)
0062 {
0063     if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
0064         struct nouveau_cli *cli = (void *)chan->user.client;
0065         struct nouveau_fence *fence = NULL;
0066         int ret;
0067
0068         ret = nouveau_fence_new(chan, false, &fence);
0069         if (!ret) {
0070             ret = nouveau_fence_wait(fence, false, false);
0071             nouveau_fence_unref(&fence);
0072         }
0073
0074         if (ret) {
0075             NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
0076                   chan->chid, nvxx_client(&cli->base)->name);
0077             return ret;
0078         }
0079     }
0080     return 0;
0081 }
0082
0083 void
0084 nouveau_channel_del(struct nouveau_channel **pchan)
0085 {
0086     struct nouveau_channel *chan = *pchan;
0087     if (chan) {
0088         struct nouveau_cli *cli = (void *)chan->user.client;
0089
0090         if (chan->fence)
0091             nouveau_fence(chan->drm)->context_del(chan);
0092
0093         if (cli)
0094             nouveau_svmm_part(chan->vmm->svmm, chan->inst);
0095
0096         nvif_object_dtor(&chan->nvsw);
0097         nvif_object_dtor(&chan->gart);
0098         nvif_object_dtor(&chan->vram);
0099         nvif_notify_dtor(&chan->kill);
0100         nvif_object_dtor(&chan->user);
0101         nvif_object_dtor(&chan->push.ctxdma);
0102         nouveau_vma_del(&chan->push.vma);
0103         nouveau_bo_unmap(chan->push.buffer);
0104         if (chan->push.buffer && chan->push.buffer->bo.pin_count)
0105             nouveau_bo_unpin(chan->push.buffer);
0106         nouveau_bo_ref(NULL, &chan->push.buffer);
0107         kfree(chan);
0108     }
0109     *pchan = NULL;
0110 }
0111
0112 static void
0113 nouveau_channel_kick(struct nvif_push *push)
0114 {
0115     struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
0116     chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
0117     FIRE_RING(chan);
0118     chan->chan._push.bgn = chan->chan._push.cur;
0119 }
0120
0121 static int
0122 nouveau_channel_wait(struct nvif_push *push, u32 size)
0123 {
0124     struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
0125     int ret;
0126     chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
0127     ret = RING_SPACE(chan, size);
0128     if (ret == 0) {
0129         chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr;
0130         chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur;
0131         chan->chan._push.cur = chan->chan._push.bgn;
0132         chan->chan._push.end = chan->chan._push.bgn + size;
0133     }
0134     return ret;
0135 }
0136
0137 static int
0138 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
0139              u32 size, struct nouveau_channel **pchan)
0140 {
0141     struct nouveau_cli *cli = (void *)device->object.client;
0142     struct nv_dma_v0 args = {};
0143     struct nouveau_channel *chan;
0144     u32 target;
0145     int ret;
0146
0147     chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
0148     if (!chan)
0149         return -ENOMEM;
0150
0151     chan->device = device;
0152     chan->drm = drm;
0153     chan->vmm = cli->svm.cli ? &cli->svm : &cli->vmm;
0154     atomic_set(&chan->killed, 0);
0155
0156     /* allocate memory for dma push buffer */
0157     target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
0158     if (nouveau_vram_pushbuf)
0159         target = NOUVEAU_GEM_DOMAIN_VRAM;
0160
0161     ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
0162                 &chan->push.buffer);
0163     if (ret == 0) {
0164         ret = nouveau_bo_pin(chan->push.buffer, target, false);
0165         if (ret == 0)
0166             ret = nouveau_bo_map(chan->push.buffer);
0167     }
0168
0169     if (ret) {
0170         nouveau_channel_del(pchan);
0171         return ret;
0172     }
0173
0174     chan->chan._push.mem.object.parent = cli->base.object.parent;
0175     chan->chan._push.mem.object.client = &cli->base;
0176     chan->chan._push.mem.object.name = "chanPush";
0177     chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
0178     chan->chan._push.wait = nouveau_channel_wait;
0179     chan->chan._push.kick = nouveau_channel_kick;
0180     chan->chan.push = &chan->chan._push;
0181
0182     /* create dma object covering the *entire* memory space that the
0183      * pushbuf lives in, this is because the GEM code requires that
0184      * we be able to call out to other (indirect) push buffers
0185      */
0186     chan->push.addr = chan->push.buffer->offset;
0187
0188     if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
0189         ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
0190                       &chan->push.vma);
0191         if (ret) {
0192             nouveau_channel_del(pchan);
0193             return ret;
0194         }
0195
0196         chan->push.addr = chan->push.vma->addr;
0197
0198         if (device->info.family >= NV_DEVICE_INFO_V0_FERMI)
0199             return 0;
0200
0201         args.target = NV_DMA_V0_TARGET_VM;
0202         args.access = NV_DMA_V0_ACCESS_VM;
0203         args.start = 0;
0204         args.limit = chan->vmm->vmm.limit - 1;
0205     } else
0206     if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) {
0207         if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
0208             /* nv04 vram pushbuf hack, retarget to its location in
0209              * the framebuffer bar rather than direct vram access..
0210              * nfi why this exists, it came from the -nv ddx.
0211              */
0212             args.target = NV_DMA_V0_TARGET_PCI;
0213             args.access = NV_DMA_V0_ACCESS_RDWR;
0214             args.start = nvxx_device(device)->func->
0215                 resource_addr(nvxx_device(device), 1);
0216             args.limit = args.start + device->info.ram_user - 1;
0217         } else {
0218             args.target = NV_DMA_V0_TARGET_VRAM;
0219             args.access = NV_DMA_V0_ACCESS_RDWR;
0220             args.start = 0;
0221             args.limit = device->info.ram_user - 1;
0222         }
0223     } else {
0224         if (chan->drm->agp.bridge) {
0225             args.target = NV_DMA_V0_TARGET_AGP;
0226             args.access = NV_DMA_V0_ACCESS_RDWR;
0227             args.start = chan->drm->agp.base;
0228             args.limit = chan->drm->agp.base +
0229                      chan->drm->agp.size - 1;
0230         } else {
0231             args.target = NV_DMA_V0_TARGET_VM;
0232             args.access = NV_DMA_V0_ACCESS_RDWR;
0233             args.start = 0;
0234             args.limit = chan->vmm->vmm.limit - 1;
0235         }
0236     }
0237
0238     ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0,
0239                    NV_DMA_FROM_MEMORY, &args, sizeof(args),
0240                    &chan->push.ctxdma);
0241     if (ret) {
0242         nouveau_channel_del(pchan);
0243         return ret;
0244     }
0245
0246     return 0;
0247 }
0248
0249 static int
0250 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
0251             u64 runlist, bool priv, struct nouveau_channel **pchan)
0252 {
0253     static const u16 oclasses[] = { AMPERE_CHANNEL_GPFIFO_B,
0254                     TURING_CHANNEL_GPFIFO_A,
0255                     VOLTA_CHANNEL_GPFIFO_A,
0256                     PASCAL_CHANNEL_GPFIFO_A,
0257                     MAXWELL_CHANNEL_GPFIFO_A,
0258                     KEPLER_CHANNEL_GPFIFO_B,
0259                     KEPLER_CHANNEL_GPFIFO_A,
0260                     FERMI_CHANNEL_GPFIFO,
0261                     G82_CHANNEL_GPFIFO,
0262                     NV50_CHANNEL_GPFIFO,
0263                     0 };
0264     const u16 *oclass = oclasses;
0265     union {
0266         struct nv50_channel_gpfifo_v0 nv50;
0267         struct fermi_channel_gpfifo_v0 fermi;
0268         struct kepler_channel_gpfifo_a_v0 kepler;
0269         struct volta_channel_gpfifo_a_v0 volta;
0270     } args;
0271     struct nouveau_channel *chan;
0272     u32 size;
0273     int ret;
0274
0275     /* allocate dma push buffer */
0276     ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
0277     *pchan = chan;
0278     if (ret)
0279         return ret;
0280
0281     /* create channel object */
0282     do {
0283         if (oclass[0] >= VOLTA_CHANNEL_GPFIFO_A) {
0284             args.volta.version = 0;
0285             args.volta.ilength = 0x02000;
0286             args.volta.ioffset = 0x10000 + chan->push.addr;
0287             args.volta.runlist = runlist;
0288             args.volta.vmm = nvif_handle(&chan->vmm->vmm.object);
0289             args.volta.priv = priv;
0290             size = sizeof(args.volta);
0291         } else
0292         if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
0293             args.kepler.version = 0;
0294             args.kepler.ilength = 0x02000;
0295             args.kepler.ioffset = 0x10000 + chan->push.addr;
0296             args.kepler.runlist = runlist;
0297             args.kepler.vmm = nvif_handle(&chan->vmm->vmm.object);
0298             args.kepler.priv = priv;
0299             size = sizeof(args.kepler);
0300         } else
0301         if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
0302             args.fermi.version = 0;
0303             args.fermi.ilength = 0x02000;
0304             args.fermi.ioffset = 0x10000 + chan->push.addr;
0305             args.fermi.vmm = nvif_handle(&chan->vmm->vmm.object);
0306             size = sizeof(args.fermi);
0307         } else {
0308             args.nv50.version = 0;
0309             args.nv50.ilength = 0x02000;
0310             args.nv50.ioffset = 0x10000 + chan->push.addr;
0311             args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
0312             args.nv50.vmm = nvif_handle(&chan->vmm->vmm.object);
0313             size = sizeof(args.nv50);
0314         }
0315
0316         ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0,
0317                        *oclass++, &args, size, &chan->user);
0318         if (ret == 0) {
0319             if (chan->user.oclass >= VOLTA_CHANNEL_GPFIFO_A) {
0320                 chan->chid = args.volta.chid;
0321                 chan->inst = args.volta.inst;
0322                 chan->token = args.volta.token;
0323             } else
0324             if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) {
0325                 chan->chid = args.kepler.chid;
0326                 chan->inst = args.kepler.inst;
0327             } else
0328             if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
0329                 chan->chid = args.fermi.chid;
0330             } else {
0331                 chan->chid = args.nv50.chid;
0332             }
0333             return ret;
0334         }
0335     } while (*oclass);
0336
0337     nouveau_channel_del(pchan);
0338     return ret;
0339 }
0340
0341 static int
0342 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
0343             struct nouveau_channel **pchan)
0344 {
0345     static const u16 oclasses[] = { NV40_CHANNEL_DMA,
0346                     NV17_CHANNEL_DMA,
0347                     NV10_CHANNEL_DMA,
0348                     NV03_CHANNEL_DMA,
0349                     0 };
0350     const u16 *oclass = oclasses;
0351     struct nv03_channel_dma_v0 args;
0352     struct nouveau_channel *chan;
0353     int ret;
0354
0355     /* allocate dma push buffer */
0356     ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
0357     *pchan = chan;
0358     if (ret)
0359         return ret;
0360
0361     /* create channel object */
0362     args.version = 0;
0363     args.pushbuf = nvif_handle(&chan->push.ctxdma);
0364     args.offset = chan->push.addr;
0365
0366     do {
0367         ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0,
0368                        *oclass++, &args, sizeof(args),
0369                        &chan->user);
0370         if (ret == 0) {
0371             chan->chid = args.chid;
0372             return ret;
0373         }
0374     } while (ret && *oclass);
0375
0376     nouveau_channel_del(pchan);
0377     return ret;
0378 }
0379
0380 static int
0381 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
0382 {
0383     struct nvif_device *device = chan->device;
0384     struct nouveau_drm *drm = chan->drm;
0385     struct nv_dma_v0 args = {};
0386     int ret, i;
0387
0388     ret = nvif_object_map(&chan->user, NULL, 0);
0389     if (ret)
0390         return ret;
0391
0392     if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO &&
0393         chan->user.oclass < AMPERE_CHANNEL_GPFIFO_B) {
0394         ret = nvif_notify_ctor(&chan->user, "abi16ChanKilled",
0395                        nouveau_channel_killed,
0396                        true, NV906F_V0_NTFY_KILLED,
0397                        NULL, 0, 0, &chan->kill);
0398         if (ret == 0)
0399             ret = nvif_notify_get(&chan->kill);
0400         if (ret) {
0401             NV_ERROR(drm, "Failed to request channel kill "
0402                       "notification: %d\n", ret);
0403             return ret;
0404         }
0405     }
0406
0407     /* allocate dma objects to cover all allowed vram, and gart */
0408     if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
0409         if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
0410             args.target = NV_DMA_V0_TARGET_VM;
0411             args.access = NV_DMA_V0_ACCESS_VM;
0412             args.start = 0;
0413             args.limit = chan->vmm->vmm.limit - 1;
0414         } else {
0415             args.target = NV_DMA_V0_TARGET_VRAM;
0416             args.access = NV_DMA_V0_ACCESS_RDWR;
0417             args.start = 0;
0418             args.limit = device->info.ram_user - 1;
0419         }
0420
0421         ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram,
0422                        NV_DMA_IN_MEMORY, &args, sizeof(args),
0423                        &chan->vram);
0424         if (ret)
0425             return ret;
0426
0427         if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
0428             args.target = NV_DMA_V0_TARGET_VM;
0429             args.access = NV_DMA_V0_ACCESS_VM;
0430             args.start = 0;
0431             args.limit = chan->vmm->vmm.limit - 1;
0432         } else
0433         if (chan->drm->agp.bridge) {
0434             args.target = NV_DMA_V0_TARGET_AGP;
0435             args.access = NV_DMA_V0_ACCESS_RDWR;
0436             args.start = chan->drm->agp.base;
0437             args.limit = chan->drm->agp.base +
0438                      chan->drm->agp.size - 1;
0439         } else {
0440             args.target = NV_DMA_V0_TARGET_VM;
0441             args.access = NV_DMA_V0_ACCESS_RDWR;
0442             args.start = 0;
0443             args.limit = chan->vmm->vmm.limit - 1;
0444         }
0445
0446         ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart,
0447                        NV_DMA_IN_MEMORY, &args, sizeof(args),
0448                        &chan->gart);
0449         if (ret)
0450             return ret;
0451     }
0452
0453     /* initialise dma tracking parameters */
0454     switch (chan->user.oclass & 0x00ff) {
0455     case 0x006b:
0456     case 0x006e:
0457         chan->user_put = 0x40;
0458         chan->user_get = 0x44;
0459         chan->dma.max = (0x10000 / 4) - 2;
0460         break;
0461     default:
0462         chan->user_put = 0x40;
0463         chan->user_get = 0x44;
0464         chan->user_get_hi = 0x60;
0465         chan->dma.ib_base =  0x10000 / 4;
0466         chan->dma.ib_max  = (0x02000 / 8) - 1;
0467         chan->dma.ib_put  = 0;
0468         chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
0469         chan->dma.max = chan->dma.ib_base;
0470         break;
0471     }
0472
0473     chan->dma.put = 0;
0474     chan->dma.cur = chan->dma.put;
0475     chan->dma.free = chan->dma.max - chan->dma.cur;
0476
0477     ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS);
0478     if (ret)
0479         return ret;
0480
0481     for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
0482         PUSH_DATA(chan->chan.push, 0x00000000);
0483
0484     /* allocate software object class (used for fences on <= nv05) */
0485     if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
0486         ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e,
0487                        NVIF_CLASS_SW_NV04,
0488                        NULL, 0, &chan->nvsw);
0489         if (ret)
0490             return ret;
0491
0492         ret = PUSH_WAIT(chan->chan.push, 2);
0493         if (ret)
0494             return ret;
0495
0496         PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
0497         PUSH_KICK(chan->chan.push);
0498     }
0499
0500     /* initialise synchronisation */
0501     return nouveau_fence(chan->drm)->context_new(chan);
0502 }
0503
0504 int
0505 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
0506             u32 arg0, u32 arg1, bool priv,
0507             struct nouveau_channel **pchan)
0508 {
0509     struct nouveau_cli *cli = (void *)device->object.client;
0510     int ret;
0511
0512     /* hack until fencenv50 is fixed, and agp access relaxed */
0513     ret = nouveau_channel_ind(drm, device, arg0, priv, pchan);
0514     if (ret) {
0515         NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
0516         ret = nouveau_channel_dma(drm, device, pchan);
0517         if (ret) {
0518             NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
0519             return ret;
0520         }
0521     }
0522
0523     ret = nouveau_channel_init(*pchan, arg0, arg1);
0524     if (ret) {
0525         NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
0526         nouveau_channel_del(pchan);
0527         return ret;
0528     }
0529
0530     ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
0531     if (ret)
0532         nouveau_channel_del(pchan);
0533
0534     return ret;
0535 }
0536
0537 int
0538 nouveau_channels_init(struct nouveau_drm *drm)
0539 {
0540     struct {
0541         struct nv_device_info_v1 m;
0542         struct {
0543             struct nv_device_info_v1_data channels;
0544         } v;
0545     } args = {
0546         .m.version = 1,
0547         .m.count = sizeof(args.v) / sizeof(args.v.channels),
0548         .v.channels.mthd = NV_DEVICE_HOST_CHANNELS,
0549     };
0550     struct nvif_object *device = &drm->client.device.object;
0551     int ret;
0552
0553     ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
0554     if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
0555         return -ENODEV;
0556
0557     drm->chan.nr = args.v.channels.data;
0558     drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr);
0559     return 0;
0560 }