nvkm/subdev/clk.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NVKM_CLK_H__
0003 #define __NVKM_CLK_H__
0004 #include <core/subdev.h>
0005 #include <subdev/pci.h>
0006 struct nvbios_pll;
0007 struct nvkm_pll_vals;
0008
0009 #define NVKM_CLK_CSTATE_DEFAULT -1 /* POSTed default */
0010 #define NVKM_CLK_CSTATE_BASE    -2 /* pstate base */
0011 #define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */
0012
0013 enum nv_clk_src {
0014     nv_clk_src_crystal,
0015     nv_clk_src_href,
0016
0017     nv_clk_src_hclk,
0018     nv_clk_src_hclkm3,
0019     nv_clk_src_hclkm3d2,
0020     nv_clk_src_hclkm2d3, /* NVAA */
0021     nv_clk_src_hclkm4, /* NVAA */
0022     nv_clk_src_cclk, /* NVAA */
0023
0024     nv_clk_src_host,
0025
0026     nv_clk_src_sppll0,
0027     nv_clk_src_sppll1,
0028
0029     nv_clk_src_mpllsrcref,
0030     nv_clk_src_mpllsrc,
0031     nv_clk_src_mpll,
0032     nv_clk_src_mdiv,
0033
0034     nv_clk_src_core,
0035     nv_clk_src_core_intm,
0036     nv_clk_src_shader,
0037
0038     nv_clk_src_mem,
0039
0040     nv_clk_src_gpc,
0041     nv_clk_src_rop,
0042     nv_clk_src_hubk01,
0043     nv_clk_src_hubk06,
0044     nv_clk_src_hubk07,
0045     nv_clk_src_copy,
0046     nv_clk_src_pmu,
0047     nv_clk_src_disp,
0048     nv_clk_src_vdec,
0049
0050     nv_clk_src_dom6,
0051
0052     nv_clk_src_max,
0053 };
0054
0055 struct nvkm_cstate {
0056     struct list_head head;
0057     u8  voltage;
0058     u32 domain[nv_clk_src_max];
0059     u8  id;
0060 };
0061
0062 struct nvkm_pstate {
0063     struct list_head head;
0064     struct list_head list; /* c-states */
0065     struct nvkm_cstate base;
0066     u8 pstate;
0067     u8 fanspeed;
0068     enum nvkm_pcie_speed pcie_speed;
0069     u8 pcie_width;
0070 };
0071
0072 struct nvkm_domain {
0073     enum nv_clk_src name;
0074     u8 bios; /* 0xff for none */
0075 #define NVKM_CLK_DOM_FLAG_CORE    0x01
0076 #define NVKM_CLK_DOM_FLAG_VPSTATE 0x02
0077     u8 flags;
0078     const char *mname;
0079     int mdiv;
0080 };
0081
0082 struct nvkm_clk {
0083     const struct nvkm_clk_func *func;
0084     struct nvkm_subdev subdev;
0085
0086     const struct nvkm_domain *domains;
0087     struct nvkm_pstate bstate;
0088
0089     struct list_head states;
0090     int state_nr;
0091
0092     struct work_struct work;
0093     wait_queue_head_t wait;
0094     atomic_t waiting;
0095
0096     int pwrsrc;
0097     int pstate; /* current */
0098     int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
0099     int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
0100     int astate; /* perfmon adjustment (base) */
0101     int dstate; /* display adjustment (min+) */
0102     u8  temp;
0103
0104     bool allow_reclock;
0105 #define NVKM_CLK_BOOST_NONE 0x0
0106 #define NVKM_CLK_BOOST_BIOS 0x1
0107 #define NVKM_CLK_BOOST_FULL 0x2
0108     u8  boost_mode;
0109     u32 base_khz;
0110     u32 boost_khz;
0111
0112     /*XXX: die, these are here *only* to support the completely
0113      *     bat-shit insane what-was-nouveau_hw.c code
0114      */
0115     int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
0116             struct nvkm_pll_vals *pv);
0117     int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
0118 };
0119
0120 int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src);
0121 int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
0122 int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
0123 int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
0124 int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature);
0125 int nvkm_clk_pwrsrc(struct nvkm_device *);
0126
0127 int nv04_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0128 int nv40_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0129 int nv50_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0130 int g84_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0131 int mcp77_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0132 int gt215_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0133 int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0134 int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0135 int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0136 int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
0137 #endif