subdev/bios/pll.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NVBIOS_PLL_H__
0003 #define __NVBIOS_PLL_H__
0004 /*XXX: kill me */
0005 struct nvkm_pll_vals {
0006     union {
0007         struct {
0008 #ifdef __BIG_ENDIAN
0009             uint8_t N1, M1, N2, M2;
0010 #else
0011             uint8_t M1, N1, M2, N2;
0012 #endif
0013         };
0014         struct {
0015             uint16_t NM1, NM2;
0016         } __attribute__((packed));
0017     };
0018     int log2P;
0019
0020     int refclk;
0021 };
0022
0023 /* these match types in pll limits table version 0x40,
0024  * nvkm uses them on all chipsets internally where a
0025  * specific pll needs to be referenced, but the exact
0026  * register isn't known.
0027  */
0028 enum nvbios_pll_type {
0029     PLL_CORE   = 0x01,
0030     PLL_SHADER = 0x02,
0031     PLL_UNK03  = 0x03,
0032     PLL_MEMORY = 0x04,
0033     PLL_VDEC   = 0x05,
0034     PLL_UNK40  = 0x40,
0035     PLL_UNK41  = 0x41,
0036     PLL_UNK42  = 0x42,
0037     PLL_VPLL0  = 0x80,
0038     PLL_VPLL1  = 0x81,
0039     PLL_VPLL2  = 0x82,
0040     PLL_VPLL3  = 0x83,
0041     PLL_MAX    = 0xff
0042 };
0043
0044 struct nvbios_pll {
0045     enum nvbios_pll_type type;
0046     u32 reg;
0047     u32 refclk;
0048
0049     u8 min_p;
0050     u8 max_p;
0051     u8 bias_p;
0052
0053     /*
0054      * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
0055      * value) is no different to 6 (at least for vplls) so allowing the MNP
0056      * calc to use 7 causes the generated clock to be out by a factor of 2.
0057      * however, max_log2p cannot be fixed-up during parsing as the
0058      * unmodified max_log2p value is still needed for setting mplls, hence
0059      * an additional max_usable_log2p member
0060      */
0061     u8 max_p_usable;
0062
0063     struct {
0064         u32 min_freq;
0065         u32 max_freq;
0066         u32 min_inputfreq;
0067         u32 max_inputfreq;
0068         u8  min_m;
0069         u8  max_m;
0070         u8  min_n;
0071         u8  max_n;
0072     } vco1, vco2;
0073 };
0074
0075 int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);
0076 #endif