nvkm/core/tegra.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NVKM_DEVICE_TEGRA_H__
0003 #define __NVKM_DEVICE_TEGRA_H__
0004 #include <core/device.h>
0005 #include <core/mm.h>
0006
0007 struct nvkm_device_tegra {
0008     const struct nvkm_device_tegra_func *func;
0009     struct nvkm_device device;
0010     struct platform_device *pdev;
0011     int irq;
0012
0013     struct reset_control *rst;
0014     struct clk *clk;
0015     struct clk *clk_ref;
0016     struct clk *clk_pwr;
0017
0018     struct regulator *vdd;
0019
0020     struct {
0021         /*
0022          * Protects accesses to mm from subsystems
0023          */
0024         struct mutex mutex;
0025
0026         struct nvkm_mm mm;
0027         struct iommu_domain *domain;
0028         unsigned long pgshift;
0029     } iommu;
0030
0031     int gpu_speedo;
0032     int gpu_speedo_id;
0033 };
0034
0035 struct nvkm_device_tegra_func {
0036     /*
0037      * If an IOMMU is used, indicates which address bit will trigger a
0038      * IOMMU translation when set (when this bit is not set, IOMMU is
0039      * bypassed). A value of 0 means an IOMMU is never used.
0040      */
0041     u8 iommu_bit;
0042     /*
0043      * Whether the chip requires a reference clock
0044      */
0045     bool require_ref_clk;
0046     /*
0047      * Whether the chip requires the VDD regulator
0048      */
0049     bool require_vdd;
0050 };
0051
0052 int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
0053               struct platform_device *,
0054               const char *cfg, const char *dbg,
0055               bool detect, bool mmio, u64 subdev_mask,
0056               struct nvkm_device **);
0057 #endif