include/nvif/cl5070.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NVIF_CL5070_H__
0003 #define __NVIF_CL5070_H__
0004
0005 #define NV50_DISP_MTHD                                                     0x00
0006
0007 struct nv50_disp_mthd_v0 {
0008     __u8  version;
0009 #define NV50_DISP_SCANOUTPOS                                               0x00
0010     __u8  method;
0011     __u8  head;
0012     __u8  pad03[5];
0013 };
0014
0015 struct nv50_disp_scanoutpos_v0 {
0016     __u8  version;
0017     __u8  pad01[7];
0018     __s64 time[2];
0019     __u16 vblanks;
0020     __u16 vblanke;
0021     __u16 vtotal;
0022     __u16 vline;
0023     __u16 hblanks;
0024     __u16 hblanke;
0025     __u16 htotal;
0026     __u16 hline;
0027 };
0028
0029 struct nv50_disp_mthd_v1 {
0030     __u8  version;
0031 #define NV50_DISP_MTHD_V1_ACQUIRE                                          0x01
0032 #define NV50_DISP_MTHD_V1_RELEASE                                          0x02
0033 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
0034 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
0035 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
0036 #define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK                                  0x25
0037 #define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI                                  0x26
0038     __u8  method;
0039     __u16 hasht;
0040     __u16 hashm;
0041     __u8  pad06[2];
0042 };
0043
0044 struct nv50_disp_acquire_v0 {
0045     __u8  version;
0046     __u8  or;
0047     __u8  link;
0048     __u8  hda;
0049     __u8  pad04[4];
0050 };
0051
0052 struct nv50_disp_sor_hda_eld_v0 {
0053     __u8  version;
0054     __u8  pad01[7];
0055     __u8  data[];
0056 };
0057
0058 struct nv50_disp_sor_hdmi_pwr_v0 {
0059     __u8  version;
0060     __u8  state;
0061     __u8  max_ac_packet;
0062     __u8  rekey;
0063     __u8  avi_infoframe_length;
0064     __u8  vendor_infoframe_length;
0065 #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0)
0066 #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1)
0067     __u8  scdc;
0068     __u8  pad07[1];
0069 };
0070
0071 struct nv50_disp_sor_lvds_script_v0 {
0072     __u8  version;
0073     __u8  pad01[1];
0074     __u16 script;
0075     __u8  pad04[4];
0076 };
0077
0078 struct nv50_disp_sor_dp_mst_link_v0 {
0079     __u8  version;
0080     __u8  state;
0081     __u8  pad02[6];
0082 };
0083
0084 struct nv50_disp_sor_dp_mst_vcpi_v0 {
0085     __u8  version;
0086     __u8  pad01[1];
0087     __u8  start_slot;
0088     __u8  num_slots;
0089     __u16 pbn;
0090     __u16 aligned_pbn;
0091 };
0092 #endif