include/nvif/cl0080.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NVIF_CL0080_H__
0003 #define __NVIF_CL0080_H__
0004
0005 struct nv_device_v0 {
0006     __u8  version;
0007     __u8  priv;
0008     __u8  pad02[6];
0009     __u64 device;   /* device identifier, ~0 for client default */
0010 };
0011
0012 #define NV_DEVICE_V0_INFO                                                  0x00
0013 #define NV_DEVICE_V0_TIME                                                  0x01
0014
0015 struct nv_device_info_v0 {
0016     __u8  version;
0017 #define NV_DEVICE_INFO_V0_IGP                                              0x00
0018 #define NV_DEVICE_INFO_V0_PCI                                              0x01
0019 #define NV_DEVICE_INFO_V0_AGP                                              0x02
0020 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
0021 #define NV_DEVICE_INFO_V0_SOC                                              0x04
0022     __u8  platform;
0023     __u16 chipset;  /* from NV_PMC_BOOT_0 */
0024     __u8  revision; /* from NV_PMC_BOOT_0 */
0025 #define NV_DEVICE_INFO_V0_TNT                                              0x01
0026 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
0027 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
0028 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
0029 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
0030 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
0031 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
0032 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
0033 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
0034 #define NV_DEVICE_INFO_V0_PASCAL                                           0x0a
0035 #define NV_DEVICE_INFO_V0_VOLTA                                            0x0b
0036 #define NV_DEVICE_INFO_V0_TURING                                           0x0c
0037 #define NV_DEVICE_INFO_V0_AMPERE                                           0x0d
0038     __u8  family;
0039     __u8  pad06[2];
0040     __u64 ram_size;
0041     __u64 ram_user;
0042     char  chip[16];
0043     char  name[64];
0044 };
0045
0046 struct nv_device_info_v1 {
0047     __u8  version;
0048     __u8  count;
0049     __u8  pad02[6];
0050     struct nv_device_info_v1_data {
0051         __u64 mthd; /* NV_DEVICE_INFO_* (see below). */
0052         __u64 data;
0053     } data[];
0054 };
0055
0056 struct nv_device_time_v0 {
0057     __u8  version;
0058     __u8  pad01[7];
0059     __u64 time;
0060 };
0061
0062 #define NV_DEVICE_INFO_UNIT                               (0xffffffffULL << 32)
0063 #define NV_DEVICE_INFO(n)                          ((n) | (0x00000000ULL << 32))
0064 #define NV_DEVICE_HOST(n)                          ((n) | (0x00000001ULL << 32))
0065
0066 /* This will be returned in the mthd field for unsupported queries. */
0067 #define NV_DEVICE_INFO_INVALID                                           ~0ULL
0068
0069 /* Returns the number of available runlists. */
0070 #define NV_DEVICE_HOST_RUNLISTS                       NV_DEVICE_HOST(0x00000000)
0071 /* Returns the number of available channels. */
0072 #define NV_DEVICE_HOST_CHANNELS                       NV_DEVICE_HOST(0x00000001)
0073
0074 /* Returns a mask of available engine types on runlist(data). */
0075 #define NV_DEVICE_HOST_RUNLIST_ENGINES                NV_DEVICE_HOST(0x00000100)
0076 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SW                            0x00000001
0077 #define NV_DEVICE_HOST_RUNLIST_ENGINES_GR                            0x00000002
0078 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MPEG                          0x00000004
0079 #define NV_DEVICE_HOST_RUNLIST_ENGINES_ME                            0x00000008
0080 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CIPHER                        0x00000010
0081 #define NV_DEVICE_HOST_RUNLIST_ENGINES_BSP                           0x00000020
0082 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VP                            0x00000040
0083 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CE                            0x00000080
0084 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC                           0x00000100
0085 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD                         0x00000200
0086 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC                        0x00000400
0087 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP                         0x00000800
0088 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSENC                         0x00001000
0089 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VIC                           0x00002000
0090 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2                          0x00004000
0091 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC                         0x00008000
0092 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC                         0x00010000
0093 #endif