include/nvif/cl0002.h

0001 /* SPDX-License-Identifier: MIT */
0002 #ifndef __NVIF_CL0002_H__
0003 #define __NVIF_CL0002_H__
0004
0005 struct nv_dma_v0 {
0006     __u8  version;
0007 #define NV_DMA_V0_TARGET_VM                                                0x00
0008 #define NV_DMA_V0_TARGET_VRAM                                              0x01
0009 #define NV_DMA_V0_TARGET_PCI                                               0x02
0010 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
0011 #define NV_DMA_V0_TARGET_AGP                                               0x04
0012     __u8  target;
0013 #define NV_DMA_V0_ACCESS_VM                                                0x00
0014 #define NV_DMA_V0_ACCESS_RD                                                0x01
0015 #define NV_DMA_V0_ACCESS_WR                                                0x02
0016 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
0017     __u8  access;
0018     __u8  pad03[5];
0019     __u64 start;
0020     __u64 limit;
0021     /* ... chipset-specific class data */
0022 };
0023
0024 struct nv50_dma_v0 {
0025     __u8  version;
0026 #define NV50_DMA_V0_PRIV_VM                                                0x00
0027 #define NV50_DMA_V0_PRIV_US                                                0x01
0028 #define NV50_DMA_V0_PRIV__S                                                0x02
0029     __u8  priv;
0030 #define NV50_DMA_V0_PART_VM                                                0x00
0031 #define NV50_DMA_V0_PART_256                                               0x01
0032 #define NV50_DMA_V0_PART_1KB                                               0x02
0033     __u8  part;
0034 #define NV50_DMA_V0_COMP_NONE                                              0x00
0035 #define NV50_DMA_V0_COMP_1                                                 0x01
0036 #define NV50_DMA_V0_COMP_2                                                 0x02
0037 #define NV50_DMA_V0_COMP_VM                                                0x03
0038     __u8  comp;
0039 #define NV50_DMA_V0_KIND_PITCH                                             0x00
0040 #define NV50_DMA_V0_KIND_VM                                                0x7f
0041     __u8  kind;
0042     __u8  pad05[3];
0043 };
0044
0045 struct gf100_dma_v0 {
0046     __u8  version;
0047 #define GF100_DMA_V0_PRIV_VM                                               0x00
0048 #define GF100_DMA_V0_PRIV_US                                               0x01
0049 #define GF100_DMA_V0_PRIV__S                                               0x02
0050     __u8  priv;
0051 #define GF100_DMA_V0_KIND_PITCH                                            0x00
0052 #define GF100_DMA_V0_KIND_VM                                               0xff
0053     __u8  kind;
0054     __u8  pad03[5];
0055 };
0056
0057 struct gf119_dma_v0 {
0058     __u8  version;
0059 #define GF119_DMA_V0_PAGE_LP                                               0x00
0060 #define GF119_DMA_V0_PAGE_SP                                               0x01
0061     __u8  page;
0062 #define GF119_DMA_V0_KIND_PITCH                                            0x00
0063 #define GF119_DMA_V0_KIND_VM                                               0xff
0064     __u8  kind;
0065     __u8  pad03[5];
0066 };
0067 #endif