nvhw/class/cla0b5.h

0001 /*******************************************************************************
0002     Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
0003
0004     Permission is hereby granted, free of charge, to any person obtaining a
0005     copy of this software and associated documentation files (the "Software"),
0006     to deal in the Software without restriction, including without limitation
0007     the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008     and/or sell copies of the Software, and to permit persons to whom the
0009     Software is furnished to do so, subject to the following conditions:
0010
0011     The above copyright notice and this permission notice shall be included in
0012     all copies or substantial portions of the Software.
0013
0014     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015     IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016     FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017     THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018     LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0019     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0020     DEALINGS IN THE SOFTWARE.
0021
0022 *******************************************************************************/
0023
0024 #ifndef _cla0b5_h_
0025 #define _cla0b5_h_
0026
0027 #define NVA0B5_SET_SRC_PHYS_MODE                                                (0x00000260)
0028 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET                                         1:0
0029 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB                                (0x00000000)
0030 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM                         (0x00000001)
0031 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM                      (0x00000002)
0032 #define NVA0B5_SET_DST_PHYS_MODE                                                (0x00000264)
0033 #define NVA0B5_SET_DST_PHYS_MODE_TARGET                                         1:0
0034 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB                                (0x00000000)
0035 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM                         (0x00000001)
0036 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM                      (0x00000002)
0037 #define NVA0B5_LAUNCH_DMA                                                       (0x00000300)
0038 #define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE                                    1:0
0039 #define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE                               (0x00000000)
0040 #define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED                          (0x00000001)
0041 #define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED                      (0x00000002)
0042 #define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE                                          2:2
0043 #define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE                                    (0x00000000)
0044 #define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE                                     (0x00000001)
0045 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE                                        4:3
0046 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE                                   (0x00000000)
0047 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE             (0x00000001)
0048 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE            (0x00000002)
0049 #define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE                                        6:5
0050 #define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                   (0x00000000)
0051 #define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING                               (0x00000001)
0052 #define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING                           (0x00000002)
0053 #define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT                                     7:7
0054 #define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR                         (0x00000000)
0055 #define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH                               (0x00000001)
0056 #define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT                                     8:8
0057 #define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                         (0x00000000)
0058 #define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                               (0x00000001)
0059 #define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE                                     9:9
0060 #define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE                               (0x00000000)
0061 #define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE                                (0x00000001)
0062 #define NVA0B5_LAUNCH_DMA_REMAP_ENABLE                                          10:10
0063 #define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE                                    (0x00000000)
0064 #define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE                                     (0x00000001)
0065 #define NVA0B5_LAUNCH_DMA_BYPASS_L2                                             11:11
0066 #define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING                             (0x00000000)
0067 #define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE                              (0x00000001)
0068 #define NVA0B5_LAUNCH_DMA_SRC_TYPE                                              12:12
0069 #define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL                                      (0x00000000)
0070 #define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL                                     (0x00000001)
0071 #define NVA0B5_LAUNCH_DMA_DST_TYPE                                              13:13
0072 #define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL                                      (0x00000000)
0073 #define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL                                     (0x00000001)
0074 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION                                   17:14
0075 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN                              (0x00000000)
0076 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX                              (0x00000001)
0077 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR                              (0x00000002)
0078 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND                              (0x00000003)
0079 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR                               (0x00000004)
0080 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD                              (0x00000005)
0081 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC                               (0x00000006)
0082 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC                               (0x00000007)
0083 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD                              (0x0000000A)
0084 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN                              (0x0000000B)
0085 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX                              (0x0000000C)
0086 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL                              (0x0000000D)
0087 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL                              (0x0000000E)
0088 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN                              18:18
0089 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED                       (0x00000000)
0090 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED                     (0x00000001)
0091 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE                            19:19
0092 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE                      (0x00000000)
0093 #define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE                       (0x00000001)
0094 #define NVA0B5_OFFSET_IN_UPPER                                                  (0x00000400)
0095 #define NVA0B5_OFFSET_IN_UPPER_UPPER                                            7:0
0096 #define NVA0B5_OFFSET_IN_LOWER                                                  (0x00000404)
0097 #define NVA0B5_OFFSET_IN_LOWER_VALUE                                            31:0
0098 #define NVA0B5_OFFSET_OUT_UPPER                                                 (0x00000408)
0099 #define NVA0B5_OFFSET_OUT_UPPER_UPPER                                           7:0
0100 #define NVA0B5_OFFSET_OUT_LOWER                                                 (0x0000040C)
0101 #define NVA0B5_OFFSET_OUT_LOWER_VALUE                                           31:0
0102 #define NVA0B5_PITCH_IN                                                         (0x00000410)
0103 #define NVA0B5_PITCH_IN_VALUE                                                   31:0
0104 #define NVA0B5_PITCH_OUT                                                        (0x00000414)
0105 #define NVA0B5_PITCH_OUT_VALUE                                                  31:0
0106 #define NVA0B5_LINE_LENGTH_IN                                                   (0x00000418)
0107 #define NVA0B5_LINE_LENGTH_IN_VALUE                                             31:0
0108 #define NVA0B5_LINE_COUNT                                                       (0x0000041C)
0109 #define NVA0B5_LINE_COUNT_VALUE                                                 31:0
0110 #define NVA0B5_SET_REMAP_CONST_A                                                (0x00000700)
0111 #define NVA0B5_SET_REMAP_CONST_A_V                                              31:0
0112 #define NVA0B5_SET_REMAP_CONST_B                                                (0x00000704)
0113 #define NVA0B5_SET_REMAP_CONST_B_V                                              31:0
0114 #define NVA0B5_SET_REMAP_COMPONENTS                                             (0x00000708)
0115 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X                                       2:0
0116 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X                                 (0x00000000)
0117 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y                                 (0x00000001)
0118 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z                                 (0x00000002)
0119 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W                                 (0x00000003)
0120 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A                               (0x00000004)
0121 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B                               (0x00000005)
0122 #define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE                              (0x00000006)
0123 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y                                       6:4
0124 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X                                 (0x00000000)
0125 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y                                 (0x00000001)
0126 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z                                 (0x00000002)
0127 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W                                 (0x00000003)
0128 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A                               (0x00000004)
0129 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B                               (0x00000005)
0130 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE                              (0x00000006)
0131 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z                                       10:8
0132 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X                                 (0x00000000)
0133 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y                                 (0x00000001)
0134 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z                                 (0x00000002)
0135 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W                                 (0x00000003)
0136 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A                               (0x00000004)
0137 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B                               (0x00000005)
0138 #define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE                              (0x00000006)
0139 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W                                       14:12
0140 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X                                 (0x00000000)
0141 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y                                 (0x00000001)
0142 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z                                 (0x00000002)
0143 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W                                 (0x00000003)
0144 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A                               (0x00000004)
0145 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B                               (0x00000005)
0146 #define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE                              (0x00000006)
0147 #define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE                              17:16
0148 #define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE                          (0x00000000)
0149 #define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO                          (0x00000001)
0150 #define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE                        (0x00000002)
0151 #define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR                         (0x00000003)
0152 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS                          21:20
0153 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE                      (0x00000000)
0154 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO                      (0x00000001)
0155 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE                    (0x00000002)
0156 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR                     (0x00000003)
0157 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS                          25:24
0158 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE                      (0x00000000)
0159 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO                      (0x00000001)
0160 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE                    (0x00000002)
0161 #define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR                     (0x00000003)
0162 #endif // _cla0b5_h