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0001 /*
0002  * Copyright 2018 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #include "wndw.h"
0023 #include "wimm.h"
0024 #include "handles.h"
0025 
0026 #include <nvif/class.h>
0027 #include <nvif/cl0002.h>
0028 
0029 #include <nvhw/class/cl507c.h>
0030 #include <nvhw/class/cl507e.h>
0031 #include <nvhw/class/clc37e.h>
0032 
0033 #include <drm/drm_atomic.h>
0034 #include <drm/drm_atomic_helper.h>
0035 #include <drm/drm_blend.h>
0036 #include <drm/drm_gem_atomic_helper.h>
0037 #include <drm/drm_fourcc.h>
0038 
0039 #include "nouveau_bo.h"
0040 #include "nouveau_gem.h"
0041 
0042 static void
0043 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
0044 {
0045     nvif_object_dtor(&ctxdma->object);
0046     list_del(&ctxdma->head);
0047     kfree(ctxdma);
0048 }
0049 
0050 static struct nv50_wndw_ctxdma *
0051 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb)
0052 {
0053     struct nouveau_drm *drm = nouveau_drm(fb->dev);
0054     struct nv50_wndw_ctxdma *ctxdma;
0055     u32 handle;
0056     u32 unused;
0057     u8  kind;
0058     struct {
0059         struct nv_dma_v0 base;
0060         union {
0061             struct nv50_dma_v0 nv50;
0062             struct gf100_dma_v0 gf100;
0063             struct gf119_dma_v0 gf119;
0064         };
0065     } args = {};
0066     u32 argc = sizeof(args.base);
0067     int ret;
0068 
0069     nouveau_framebuffer_get_layout(fb, &unused, &kind);
0070     handle = NV50_DISP_HANDLE_WNDW_CTX(kind);
0071 
0072     list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) {
0073         if (ctxdma->object.handle == handle)
0074             return ctxdma;
0075     }
0076 
0077     if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
0078         return ERR_PTR(-ENOMEM);
0079     list_add(&ctxdma->head, &wndw->ctxdma.list);
0080 
0081     args.base.target = NV_DMA_V0_TARGET_VRAM;
0082     args.base.access = NV_DMA_V0_ACCESS_RDWR;
0083     args.base.start  = 0;
0084     args.base.limit  = drm->client.device.info.ram_user - 1;
0085 
0086     if (drm->client.device.info.chipset < 0x80) {
0087         args.nv50.part = NV50_DMA_V0_PART_256;
0088         argc += sizeof(args.nv50);
0089     } else
0090     if (drm->client.device.info.chipset < 0xc0) {
0091         args.nv50.part = NV50_DMA_V0_PART_256;
0092         args.nv50.kind = kind;
0093         argc += sizeof(args.nv50);
0094     } else
0095     if (drm->client.device.info.chipset < 0xd0) {
0096         args.gf100.kind = kind;
0097         argc += sizeof(args.gf100);
0098     } else {
0099         args.gf119.page = GF119_DMA_V0_PAGE_LP;
0100         args.gf119.kind = kind;
0101         argc += sizeof(args.gf119);
0102     }
0103 
0104     ret = nvif_object_ctor(wndw->ctxdma.parent, "kmsFbCtxDma", handle,
0105                    NV_DMA_IN_MEMORY, &args, argc, &ctxdma->object);
0106     if (ret) {
0107         nv50_wndw_ctxdma_del(ctxdma);
0108         return ERR_PTR(ret);
0109     }
0110 
0111     return ctxdma;
0112 }
0113 
0114 int
0115 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
0116 {
0117     struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
0118     if (asyw->set.ntfy) {
0119         return wndw->func->ntfy_wait_begun(disp->sync,
0120                            asyw->ntfy.offset,
0121                            wndw->wndw.base.device);
0122     }
0123     return 0;
0124 }
0125 
0126 void
0127 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
0128             struct nv50_wndw_atom *asyw)
0129 {
0130     union nv50_wndw_atom_mask clr = {
0131         .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
0132     };
0133     if (clr.sema ) wndw->func-> sema_clr(wndw);
0134     if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
0135     if (clr.xlut ) wndw->func-> xlut_clr(wndw);
0136     if (clr.csc  ) wndw->func->  csc_clr(wndw);
0137     if (clr.image) wndw->func->image_clr(wndw);
0138 
0139     interlock[wndw->interlock.type] |= wndw->interlock.data;
0140 }
0141 
0142 void
0143 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
0144             struct nv50_wndw_atom *asyw)
0145 {
0146     if (interlock[NV50_DISP_INTERLOCK_CORE]) {
0147         asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING;
0148         asyw->image.interval = 1;
0149     }
0150 
0151     if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
0152     if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
0153     if (asyw->set.image) wndw->func->image_set(wndw, asyw);
0154 
0155     if (asyw->set.xlut ) {
0156         if (asyw->ilut) {
0157             asyw->xlut.i.offset =
0158                 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer,
0159                           asyw->ilut, asyw->xlut.i.load);
0160         }
0161         wndw->func->xlut_set(wndw, asyw);
0162     }
0163 
0164     if (asyw->set.csc  ) wndw->func->csc_set  (wndw, asyw);
0165     if (asyw->set.scale) wndw->func->scale_set(wndw, asyw);
0166     if (asyw->set.blend) wndw->func->blend_set(wndw, asyw);
0167     if (asyw->set.point) {
0168         if (asyw->set.point = false, asyw->set.mask)
0169             interlock[wndw->interlock.type] |= wndw->interlock.data;
0170         interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm;
0171 
0172         wndw->immd->point(wndw, asyw);
0173         wndw->immd->update(wndw, interlock);
0174     } else {
0175         interlock[wndw->interlock.type] |= wndw->interlock.data;
0176     }
0177 }
0178 
0179 void
0180 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
0181 {
0182     struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
0183 
0184     asyw->ntfy.handle = wndw->wndw.sync.handle;
0185     asyw->ntfy.offset = wndw->ntfy;
0186     asyw->ntfy.awaken = false;
0187     asyw->set.ntfy = true;
0188 
0189     wndw->func->ntfy_reset(disp->sync, wndw->ntfy);
0190     wndw->ntfy ^= 0x10;
0191 }
0192 
0193 static void
0194 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
0195                    struct nv50_wndw_atom *asyw,
0196                    struct nv50_head_atom *asyh)
0197 {
0198     struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
0199     NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
0200     wndw->func->release(wndw, asyw, asyh);
0201     asyw->ntfy.handle = 0;
0202     asyw->sema.handle = 0;
0203     asyw->xlut.handle = 0;
0204     memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle));
0205 }
0206 
0207 static int
0208 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
0209 {
0210     switch (asyw->state.fb->format->format) {
0211     case DRM_FORMAT_YUYV:
0212         asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8;
0213         break;
0214     case DRM_FORMAT_UYVY:
0215         asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8;
0216         break;
0217     default:
0218         WARN_ON(1);
0219         return -EINVAL;
0220     }
0221 
0222     asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601;
0223     return 0;
0224 }
0225 
0226 static int
0227 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
0228 {
0229     switch (asyw->state.fb->format->format) {
0230     case DRM_FORMAT_C8:
0231         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8;
0232         break;
0233     case DRM_FORMAT_XRGB8888:
0234     case DRM_FORMAT_ARGB8888:
0235         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8;
0236         break;
0237     case DRM_FORMAT_RGB565:
0238         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5;
0239         break;
0240     case DRM_FORMAT_XRGB1555:
0241     case DRM_FORMAT_ARGB1555:
0242         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5;
0243         break;
0244     case DRM_FORMAT_XBGR2101010:
0245     case DRM_FORMAT_ABGR2101010:
0246         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10;
0247         break;
0248     case DRM_FORMAT_XBGR8888:
0249     case DRM_FORMAT_ABGR8888:
0250         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8;
0251         break;
0252     case DRM_FORMAT_XRGB2101010:
0253     case DRM_FORMAT_ARGB2101010:
0254         asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10;
0255         break;
0256     case DRM_FORMAT_XBGR16161616F:
0257     case DRM_FORMAT_ABGR16161616F:
0258         asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16;
0259         break;
0260     default:
0261         return -EINVAL;
0262     }
0263 
0264     asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB;
0265     return 0;
0266 }
0267 
0268 static int
0269 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
0270                    struct nv50_wndw_atom *armw,
0271                    struct nv50_wndw_atom *asyw,
0272                    struct nv50_head_atom *asyh)
0273 {
0274     struct drm_framebuffer *fb = asyw->state.fb;
0275     struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
0276     uint8_t kind;
0277     uint32_t tile_mode;
0278     int ret;
0279 
0280     NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
0281 
0282     if (fb != armw->state.fb || !armw->visible || modeset) {
0283         nouveau_framebuffer_get_layout(fb, &tile_mode, &kind);
0284 
0285         asyw->image.w = fb->width;
0286         asyw->image.h = fb->height;
0287         asyw->image.kind = kind;
0288 
0289         ret = nv50_wndw_atomic_check_acquire_rgb(asyw);
0290         if (ret) {
0291             ret = nv50_wndw_atomic_check_acquire_yuv(asyw);
0292             if (ret)
0293                 return ret;
0294         }
0295 
0296         if (asyw->image.kind) {
0297             asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR;
0298             if (drm->client.device.info.chipset >= 0xc0)
0299                 asyw->image.blockh = tile_mode >> 4;
0300             else
0301                 asyw->image.blockh = tile_mode;
0302             asyw->image.blocks[0] = fb->pitches[0] / 64;
0303             asyw->image.pitch[0] = 0;
0304         } else {
0305             asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH;
0306             asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB;
0307             asyw->image.blocks[0] = 0;
0308             asyw->image.pitch[0] = fb->pitches[0];
0309         }
0310 
0311         if (!asyh->state.async_flip)
0312             asyw->image.interval = 1;
0313         else
0314             asyw->image.interval = 0;
0315 
0316         if (asyw->image.interval)
0317             asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING;
0318         else
0319             asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE;
0320 
0321         asyw->set.image = wndw->func->image_set != NULL;
0322     }
0323 
0324     if (wndw->func->scale_set) {
0325         asyw->scale.sx = asyw->state.src_x >> 16;
0326         asyw->scale.sy = asyw->state.src_y >> 16;
0327         asyw->scale.sw = asyw->state.src_w >> 16;
0328         asyw->scale.sh = asyw->state.src_h >> 16;
0329         asyw->scale.dw = asyw->state.crtc_w;
0330         asyw->scale.dh = asyw->state.crtc_h;
0331         if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale)))
0332             asyw->set.scale = true;
0333     }
0334 
0335     if (wndw->func->blend_set) {
0336         asyw->blend.depth = 255 - asyw->state.normalized_zpos;
0337         asyw->blend.k1 = asyw->state.alpha >> 8;
0338         switch (asyw->state.pixel_blend_mode) {
0339         case DRM_MODE_BLEND_PREMULTI:
0340             asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1;
0341             asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC;
0342             break;
0343         case DRM_MODE_BLEND_COVERAGE:
0344             asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC;
0345             asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC;
0346             break;
0347         case DRM_MODE_BLEND_PIXEL_NONE:
0348         default:
0349             asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1;
0350             asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1;
0351             break;
0352         }
0353         if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
0354             asyw->set.blend = true;
0355     }
0356 
0357     if (wndw->immd) {
0358         asyw->point.x = asyw->state.crtc_x;
0359         asyw->point.y = asyw->state.crtc_y;
0360         if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
0361             asyw->set.point = true;
0362     }
0363 
0364     return wndw->func->acquire(wndw, asyw, asyh);
0365 }
0366 
0367 static int
0368 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw,
0369                struct nv50_wndw_atom *armw,
0370                struct nv50_wndw_atom *asyw,
0371                struct nv50_head_atom *asyh)
0372 {
0373     struct drm_property_blob *ilut = asyh->state.degamma_lut;
0374 
0375     /* I8 format without an input LUT makes no sense, and the
0376      * HW error-checks for this.
0377      *
0378      * In order to handle legacy gamma, when there's no input
0379      * LUT we need to steal the output LUT and use it instead.
0380      */
0381     if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) {
0382         /* This should be an error, but there's legacy clients
0383          * that do a modeset before providing a gamma table.
0384          *
0385          * We keep the window disabled to avoid angering HW.
0386          */
0387         if (!(ilut = asyh->state.gamma_lut)) {
0388             asyw->visible = false;
0389             return 0;
0390         }
0391 
0392         if (wndw->func->ilut)
0393             asyh->wndw.olut |= BIT(wndw->id);
0394     } else {
0395         asyh->wndw.olut &= ~BIT(wndw->id);
0396     }
0397 
0398     if (!ilut && wndw->func->ilut_identity &&
0399         asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F &&
0400         asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) {
0401         static struct drm_property_blob dummy = {};
0402         ilut = &dummy;
0403     }
0404 
0405     /* Recalculate LUT state. */
0406     memset(&asyw->xlut, 0x00, sizeof(asyw->xlut));
0407     if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) {
0408         wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut));
0409         asyw->xlut.handle = wndw->wndw.vram.handle;
0410         asyw->xlut.i.buffer = !asyw->xlut.i.buffer;
0411         asyw->set.xlut = true;
0412     } else {
0413         asyw->clr.xlut = armw->xlut.handle != 0;
0414     }
0415 
0416     /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */
0417     if (wndw->func->olut_core &&
0418         (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle)))
0419         asyw->set.xlut = true;
0420 
0421     if (wndw->func->csc && asyh->state.ctm) {
0422         const struct drm_color_ctm *ctm = asyh->state.ctm->data;
0423         wndw->func->csc(wndw, asyw, ctm);
0424         asyw->csc.valid = true;
0425         asyw->set.csc = true;
0426     } else {
0427         asyw->csc.valid = false;
0428         asyw->clr.csc = armw->csc.valid;
0429     }
0430 
0431     /* Can't do an immediate flip while changing the LUT. */
0432     asyh->state.async_flip = false;
0433     return 0;
0434 }
0435 
0436 static int
0437 nv50_wndw_atomic_check(struct drm_plane *plane,
0438                struct drm_atomic_state *state)
0439 {
0440     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0441                                          plane);
0442     struct nouveau_drm *drm = nouveau_drm(plane->dev);
0443     struct nv50_wndw *wndw = nv50_wndw(plane);
0444     struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
0445     struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
0446     struct nv50_head_atom *harm = NULL, *asyh = NULL;
0447     bool modeset = false;
0448     int ret;
0449 
0450     NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
0451 
0452     /* Fetch the assembly state for the head the window will belong to,
0453      * and determine whether the window will be visible.
0454      */
0455     if (asyw->state.crtc) {
0456         asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
0457         if (IS_ERR(asyh))
0458             return PTR_ERR(asyh);
0459         modeset = drm_atomic_crtc_needs_modeset(&asyh->state);
0460         asyw->visible = asyh->state.active;
0461     } else {
0462         asyw->visible = false;
0463     }
0464 
0465     /* Fetch assembly state for the head the window used to belong to. */
0466     if (armw->state.crtc) {
0467         harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
0468         if (IS_ERR(harm))
0469             return PTR_ERR(harm);
0470     }
0471 
0472     /* LUT configuration can potentially cause the window to be disabled. */
0473     if (asyw->visible && wndw->func->xlut_set &&
0474         (!armw->visible ||
0475          asyh->state.color_mgmt_changed ||
0476          asyw->state.fb->format->format !=
0477          armw->state.fb->format->format)) {
0478         ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh);
0479         if (ret)
0480             return ret;
0481     }
0482 
0483     /* Calculate new window state. */
0484     if (asyw->visible) {
0485         ret = nv50_wndw_atomic_check_acquire(wndw, modeset,
0486                              armw, asyw, asyh);
0487         if (ret)
0488             return ret;
0489 
0490         asyh->wndw.mask |= BIT(wndw->id);
0491     } else
0492     if (armw->visible) {
0493         nv50_wndw_atomic_check_release(wndw, asyw, harm);
0494         harm->wndw.mask &= ~BIT(wndw->id);
0495     } else {
0496         return 0;
0497     }
0498 
0499     /* Aside from the obvious case where the window is actively being
0500      * disabled, we might also need to temporarily disable the window
0501      * when performing certain modeset operations.
0502      */
0503     if (!asyw->visible || modeset) {
0504         asyw->clr.ntfy = armw->ntfy.handle != 0;
0505         asyw->clr.sema = armw->sema.handle != 0;
0506         asyw->clr.xlut = armw->xlut.handle != 0;
0507         if (asyw->clr.xlut && asyw->visible)
0508             asyw->set.xlut = asyw->xlut.handle != 0;
0509         asyw->clr.csc  = armw->csc.valid;
0510         if (wndw->func->image_clr)
0511             asyw->clr.image = armw->image.handle[0] != 0;
0512     }
0513 
0514     return 0;
0515 }
0516 
0517 static void
0518 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
0519 {
0520     struct nouveau_drm *drm = nouveau_drm(plane->dev);
0521     struct nouveau_bo *nvbo;
0522 
0523     NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
0524     if (!old_state->fb)
0525         return;
0526 
0527     nvbo = nouveau_gem_object(old_state->fb->obj[0]);
0528     nouveau_bo_unpin(nvbo);
0529 }
0530 
0531 static int
0532 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
0533 {
0534     struct drm_framebuffer *fb = state->fb;
0535     struct nouveau_drm *drm = nouveau_drm(plane->dev);
0536     struct nv50_wndw *wndw = nv50_wndw(plane);
0537     struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
0538     struct nouveau_bo *nvbo;
0539     struct nv50_head_atom *asyh;
0540     struct nv50_wndw_ctxdma *ctxdma;
0541     int ret;
0542 
0543     NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb);
0544     if (!asyw->state.fb)
0545         return 0;
0546 
0547     nvbo = nouveau_gem_object(fb->obj[0]);
0548     ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, true);
0549     if (ret)
0550         return ret;
0551 
0552     if (wndw->ctxdma.parent) {
0553         ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
0554         if (IS_ERR(ctxdma)) {
0555             nouveau_bo_unpin(nvbo);
0556             return PTR_ERR(ctxdma);
0557         }
0558 
0559         if (asyw->visible)
0560             asyw->image.handle[0] = ctxdma->object.handle;
0561     }
0562 
0563     ret = drm_gem_plane_helper_prepare_fb(plane, state);
0564     if (ret)
0565         return ret;
0566 
0567     asyw->image.offset[0] = nvbo->offset;
0568 
0569     if (wndw->func->prepare) {
0570         asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
0571         if (IS_ERR(asyh))
0572             return PTR_ERR(asyh);
0573 
0574         wndw->func->prepare(wndw, asyh, asyw);
0575     }
0576 
0577     return 0;
0578 }
0579 
0580 static const struct drm_plane_helper_funcs
0581 nv50_wndw_helper = {
0582     .prepare_fb = nv50_wndw_prepare_fb,
0583     .cleanup_fb = nv50_wndw_cleanup_fb,
0584     .atomic_check = nv50_wndw_atomic_check,
0585 };
0586 
0587 static void
0588 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
0589                    struct drm_plane_state *state)
0590 {
0591     struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
0592     __drm_atomic_helper_plane_destroy_state(&asyw->state);
0593     kfree(asyw);
0594 }
0595 
0596 static struct drm_plane_state *
0597 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
0598 {
0599     struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
0600     struct nv50_wndw_atom *asyw;
0601     if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
0602         return NULL;
0603     __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
0604     asyw->sema = armw->sema;
0605     asyw->ntfy = armw->ntfy;
0606     asyw->ilut = NULL;
0607     asyw->xlut = armw->xlut;
0608     asyw->csc  = armw->csc;
0609     asyw->image = armw->image;
0610     asyw->point = armw->point;
0611     asyw->clr.mask = 0;
0612     asyw->set.mask = 0;
0613     return &asyw->state;
0614 }
0615 
0616 static int
0617 nv50_wndw_zpos_default(struct drm_plane *plane)
0618 {
0619     return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 :
0620            (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255;
0621 }
0622 
0623 static void
0624 nv50_wndw_reset(struct drm_plane *plane)
0625 {
0626     struct nv50_wndw_atom *asyw;
0627 
0628     if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
0629         return;
0630 
0631     if (plane->state)
0632         plane->funcs->atomic_destroy_state(plane, plane->state);
0633 
0634     __drm_atomic_helper_plane_reset(plane, &asyw->state);
0635 }
0636 
0637 static void
0638 nv50_wndw_destroy(struct drm_plane *plane)
0639 {
0640     struct nv50_wndw *wndw = nv50_wndw(plane);
0641     struct nv50_wndw_ctxdma *ctxdma, *ctxtmp;
0642 
0643     list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) {
0644         nv50_wndw_ctxdma_del(ctxdma);
0645     }
0646 
0647     nv50_dmac_destroy(&wndw->wimm);
0648     nv50_dmac_destroy(&wndw->wndw);
0649 
0650     nv50_lut_fini(&wndw->ilut);
0651 
0652     drm_plane_cleanup(&wndw->plane);
0653     kfree(wndw);
0654 }
0655 
0656 /* This function assumes the format has already been validated against the plane
0657  * and the modifier was validated against the device-wides modifier list at FB
0658  * creation time.
0659  */
0660 static bool nv50_plane_format_mod_supported(struct drm_plane *plane,
0661                         u32 format, u64 modifier)
0662 {
0663     struct nouveau_drm *drm = nouveau_drm(plane->dev);
0664     uint8_t i;
0665 
0666     if (drm->client.device.info.chipset < 0xc0) {
0667         const struct drm_format_info *info = drm_format_info(format);
0668         const uint8_t kind = (modifier >> 12) & 0xff;
0669 
0670         if (!format) return false;
0671 
0672         for (i = 0; i < info->num_planes; i++)
0673             if ((info->cpp[i] != 4) && kind != 0x70) return false;
0674     }
0675 
0676     return true;
0677 }
0678 
0679 const struct drm_plane_funcs
0680 nv50_wndw = {
0681     .update_plane = drm_atomic_helper_update_plane,
0682     .disable_plane = drm_atomic_helper_disable_plane,
0683     .destroy = nv50_wndw_destroy,
0684     .reset = nv50_wndw_reset,
0685     .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
0686     .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
0687     .format_mod_supported = nv50_plane_format_mod_supported,
0688 };
0689 
0690 static const u64 nv50_cursor_format_modifiers[] = {
0691     DRM_FORMAT_MOD_LINEAR,
0692     DRM_FORMAT_MOD_INVALID,
0693 };
0694 
0695 int
0696 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
0697            enum drm_plane_type type, const char *name, int index,
0698            const u32 *format, u32 heads,
0699            enum nv50_disp_interlock_type interlock_type, u32 interlock_data,
0700            struct nv50_wndw **pwndw)
0701 {
0702     struct nouveau_drm *drm = nouveau_drm(dev);
0703     struct nvif_mmu *mmu = &drm->client.mmu;
0704     struct nv50_disp *disp = nv50_disp(dev);
0705     struct nv50_wndw *wndw;
0706     const u64 *format_modifiers;
0707     int nformat;
0708     int ret;
0709 
0710     if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL)))
0711         return -ENOMEM;
0712     wndw->func = func;
0713     wndw->id = index;
0714     wndw->interlock.type = interlock_type;
0715     wndw->interlock.data = interlock_data;
0716 
0717     wndw->ctxdma.parent = &wndw->wndw.base.user;
0718     INIT_LIST_HEAD(&wndw->ctxdma.list);
0719 
0720     for (nformat = 0; format[nformat]; nformat++);
0721 
0722     if (type == DRM_PLANE_TYPE_CURSOR)
0723         format_modifiers = nv50_cursor_format_modifiers;
0724     else
0725         format_modifiers = nouveau_display(dev)->format_modifiers;
0726 
0727     ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, format, nformat,
0728                        format_modifiers, type, "%s-%d", name, index);
0729     if (ret) {
0730         kfree(*pwndw);
0731         *pwndw = NULL;
0732         return ret;
0733     }
0734 
0735     drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
0736 
0737     if (wndw->func->ilut) {
0738         ret = nv50_lut_init(disp, mmu, &wndw->ilut);
0739         if (ret)
0740             return ret;
0741     }
0742 
0743     if (wndw->func->blend_set) {
0744         ret = drm_plane_create_zpos_property(&wndw->plane,
0745                 nv50_wndw_zpos_default(&wndw->plane), 0, 254);
0746         if (ret)
0747             return ret;
0748 
0749         ret = drm_plane_create_alpha_property(&wndw->plane);
0750         if (ret)
0751             return ret;
0752 
0753         ret = drm_plane_create_blend_mode_property(&wndw->plane,
0754                 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
0755                 BIT(DRM_MODE_BLEND_PREMULTI) |
0756                 BIT(DRM_MODE_BLEND_COVERAGE));
0757         if (ret)
0758             return ret;
0759     } else {
0760         ret = drm_plane_create_zpos_immutable_property(&wndw->plane,
0761                 nv50_wndw_zpos_default(&wndw->plane));
0762         if (ret)
0763             return ret;
0764     }
0765 
0766     return 0;
0767 }
0768 
0769 int
0770 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
0771           struct nv50_wndw **pwndw)
0772 {
0773     struct {
0774         s32 oclass;
0775         int version;
0776         int (*new)(struct nouveau_drm *, enum drm_plane_type,
0777                int, s32, struct nv50_wndw **);
0778     } wndws[] = {
0779         { GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new },
0780         { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
0781         { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
0782         {}
0783     };
0784     struct nv50_disp *disp = nv50_disp(drm->dev);
0785     int cid, ret;
0786 
0787     cid = nvif_mclass(&disp->disp->object, wndws);
0788     if (cid < 0) {
0789         NV_ERROR(drm, "No supported window class\n");
0790         return cid;
0791     }
0792 
0793     ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw);
0794     if (ret)
0795         return ret;
0796 
0797     return nv50_wimm_init(drm, *pwndw);
0798 }
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