nouveau/dispnv50/crcc37d.c

0001 // SPDX-License-Identifier: MIT
0002 #include <drm/drm_crtc.h>
0003
0004 #include "crc.h"
0005 #include "crcc37d.h"
0006 #include "core.h"
0007 #include "disp.h"
0008 #include "head.h"
0009
0010 #include <nvif/pushc37b.h>
0011
0012 #include <nvhw/class/clc37d.h>
0013
0014 static int
0015 crcc37d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source,
0016         struct nv50_crc_notifier_ctx *ctx)
0017 {
0018     struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
0019     const int i = head->base.index;
0020     u32 crc_args = NVVAL(NVC37D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, i * 4) |
0021                NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
0022                NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |
0023                NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE);
0024     int ret;
0025
0026     switch (source) {
0027     case NV50_CRC_SOURCE_TYPE_SOR:
0028         crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or));
0029         break;
0030     case NV50_CRC_SOURCE_TYPE_PIOR:
0031         crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, PIOR(or));
0032         break;
0033     case NV50_CRC_SOURCE_TYPE_SF:
0034         crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF);
0035         break;
0036     default:
0037         break;
0038     }
0039
0040     if ((ret = PUSH_WAIT(push, 4)))
0041         return ret;
0042
0043     if (source) {
0044         PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
0045         PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
0046     } else {
0047         PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
0048         PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
0049     }
0050
0051     return 0;
0052 }
0053
0054 int crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
0055 {
0056     struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
0057     const int i = head->base.index;
0058     int ret;
0059
0060     if ((ret = PUSH_WAIT(push, 2)))
0061         return ret;
0062
0063     PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
0064     return 0;
0065 }
0066
0067 u32 crcc37d_get_entry(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx,
0068               enum nv50_crc_source source, int idx)
0069 {
0070     struct crcc37d_notifier __iomem *notifier = ctx->mem.object.map.ptr;
0071     struct crcc37d_entry __iomem *entry = &notifier->entries[idx];
0072     u32 __iomem *crc_addr;
0073
0074     if (source == NV50_CRC_SOURCE_RG)
0075         crc_addr = &entry->rg_crc;
0076     else
0077         crc_addr = &entry->output_crc[0];
0078
0079     return ioread32_native(crc_addr);
0080 }
0081
0082 bool crcc37d_ctx_finished(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
0083 {
0084     struct nouveau_drm *drm = nouveau_drm(head->base.base.dev);
0085     struct crcc37d_notifier __iomem *notifier = ctx->mem.object.map.ptr;
0086     const u32 status = ioread32_native(&notifier->status);
0087     const u32 overflow = status & 0x0000007e;
0088
0089     if (!(status & 0x00000001))
0090         return false;
0091
0092     if (overflow) {
0093         const char *engine = NULL;
0094
0095         switch (overflow) {
0096         case 0x00000004: engine = "Front End"; break;
0097         case 0x00000008: engine = "Compositor"; break;
0098         case 0x00000010: engine = "RG"; break;
0099         case 0x00000020: engine = "CRC output 1"; break;
0100         case 0x00000040: engine = "CRC output 2"; break;
0101         }
0102
0103         if (engine)
0104             NV_ERROR(drm,
0105                  "CRC notifier context for head %d overflowed on %s: %x\n",
0106                  head->base.index, engine, status);
0107         else
0108             NV_ERROR(drm,
0109                  "CRC notifier context for head %d overflowed: %x\n",
0110                  head->base.index, status);
0111     }
0112
0113     NV_DEBUG(drm, "Head %d CRC context status: %x\n",
0114          head->base.index, status);
0115
0116     return true;
0117 }
0118
0119 const struct nv50_crc_func crcc37d = {
0120     .set_src = crcc37d_set_src,
0121     .set_ctx = crcc37d_set_ctx,
0122     .get_entry = crcc37d_get_entry,
0123     .ctx_finished = crcc37d_ctx_finished,
0124     .flip_threshold = CRCC37D_FLIP_THRESHOLD,
0125     .num_entries = CRCC37D_MAX_ENTRIES,
0126     .notifier_len = sizeof(struct crcc37d_notifier),
0127 };