nouveau/dispnv50/core.c

0001 /*
0002  * Copyright 2018 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #include "core.h"
0023
0024 #include <nvif/class.h>
0025
0026 void
0027 nv50_core_del(struct nv50_core **pcore)
0028 {
0029     struct nv50_core *core = *pcore;
0030     if (core) {
0031         nv50_dmac_destroy(&core->chan);
0032         kfree(*pcore);
0033         *pcore = NULL;
0034     }
0035 }
0036
0037 int
0038 nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
0039 {
0040     struct {
0041         s32 oclass;
0042         int version;
0043         int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
0044     } cores[] = {
0045         { GA102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
0046         { TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
0047         { GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
0048         { GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
0049         { GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
0050         { GM200_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
0051         { GM107_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
0052         { GK110_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
0053         { GK104_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
0054         { GF110_DISP_CORE_CHANNEL_DMA, 0, core907d_new },
0055         { GT214_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
0056         { GT206_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
0057         { GT200_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
0058         {   G82_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
0059         {  NV50_DISP_CORE_CHANNEL_DMA, 0, core507d_new },
0060         {}
0061     };
0062     struct nv50_disp *disp = nv50_disp(drm->dev);
0063     int cid;
0064
0065     cid = nvif_mclass(&disp->disp->object, cores);
0066     if (cid < 0) {
0067         NV_ERROR(drm, "No supported core channel class\n");
0068         return cid;
0069     }
0070
0071     return cores[cid].new(drm, cores[cid].oclass, pcore);
0072 }