nouveau/dispnv04/tvnv17.h

0001 /*
0002  * Copyright (C) 2009 Francisco Jerez.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining
0006  * a copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sublicense, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the
0014  * next paragraph) shall be included in all copies or substantial
0015  * portions of the Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0018  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0020  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0021  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0022  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0023  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0024  *
0025  */
0026
0027 #ifndef __NV17_TV_H__
0028 #define __NV17_TV_H__
0029
0030 struct nv17_tv_state {
0031     uint8_t tv_enc[0x40];
0032
0033     uint32_t hfilter[4][7];
0034     uint32_t hfilter2[4][7];
0035     uint32_t vfilter[4][7];
0036
0037     uint32_t ptv_200;
0038     uint32_t ptv_204;
0039     uint32_t ptv_208;
0040     uint32_t ptv_20c;
0041     uint32_t ptv_304;
0042     uint32_t ptv_500;
0043     uint32_t ptv_504;
0044     uint32_t ptv_508;
0045     uint32_t ptv_600;
0046     uint32_t ptv_604;
0047     uint32_t ptv_608;
0048     uint32_t ptv_60c;
0049     uint32_t ptv_610;
0050     uint32_t ptv_614;
0051 };
0052
0053 enum nv17_tv_norm{
0054     TV_NORM_PAL,
0055     TV_NORM_PAL_M,
0056     TV_NORM_PAL_N,
0057     TV_NORM_PAL_NC,
0058     TV_NORM_NTSC_M,
0059     TV_NORM_NTSC_J,
0060     NUM_LD_TV_NORMS,
0061     TV_NORM_HD480I = NUM_LD_TV_NORMS,
0062     TV_NORM_HD480P,
0063     TV_NORM_HD576I,
0064     TV_NORM_HD576P,
0065     TV_NORM_HD720P,
0066     TV_NORM_HD1080I,
0067     NUM_TV_NORMS
0068 };
0069
0070 struct nv17_tv_encoder {
0071     struct nouveau_encoder base;
0072
0073     struct nv17_tv_state state;
0074     struct nv17_tv_state saved_state;
0075
0076     int overscan;
0077     int flicker;
0078     int saturation;
0079     int hue;
0080     enum nv17_tv_norm tv_norm;
0081     int subconnector;
0082     int select_subconnector;
0083     uint32_t pin_mask;
0084 };
0085 #define to_tv_enc(x) container_of(nouveau_encoder(x),       \
0086                   struct nv17_tv_encoder, base)
0087
0088 extern const char * const nv17_tv_norm_names[NUM_TV_NORMS];
0089
0090 extern struct nv17_tv_norm_params {
0091     enum {
0092         TV_ENC_MODE,
0093         CTV_ENC_MODE,
0094     } kind;
0095
0096     union {
0097         struct {
0098             int hdisplay;
0099             int vdisplay;
0100             int vrefresh; /* mHz */
0101
0102             uint8_t tv_enc[0x40];
0103         } tv_enc_mode;
0104
0105         struct {
0106             struct drm_display_mode mode;
0107
0108             uint32_t ctv_regs[38];
0109         } ctv_enc_mode;
0110     };
0111
0112 } nv17_tv_norms[NUM_TV_NORMS];
0113 #define get_tv_norm(enc) (&nv17_tv_norms[to_tv_enc(enc)->tv_norm])
0114
0115 extern const struct drm_display_mode nv17_tv_modes[];
0116
0117 static inline int interpolate(int y0, int y1, int y2, int x)
0118 {
0119     return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
0120 }
0121
0122 void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state);
0123 void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state);
0124 void nv17_tv_update_properties(struct drm_encoder *encoder);
0125 void nv17_tv_update_rescaler(struct drm_encoder *encoder);
0126 void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
0127
0128 /* TV hardware access functions */
0129
0130 static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
0131                 uint32_t val)
0132 {
0133     struct nvif_device *device = &nouveau_drm(dev)->client.device;
0134     nvif_wr32(&device->object, reg, val);
0135 }
0136
0137 static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
0138 {
0139     struct nvif_device *device = &nouveau_drm(dev)->client.device;
0140     return nvif_rd32(&device->object, reg);
0141 }
0142
0143 static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
0144                    uint8_t val)
0145 {
0146     nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
0147     nv_write_ptv(dev, NV_PTV_TV_DATA, val);
0148 }
0149
0150 static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg)
0151 {
0152     nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
0153     return nv_read_ptv(dev, NV_PTV_TV_DATA);
0154 }
0155
0156 #define nv_load_ptv(dev, state, reg) \
0157     nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, state->ptv_##reg)
0158 #define nv_save_ptv(dev, state, reg) \
0159     state->ptv_##reg = nv_read_ptv(dev, NV_PTV_OFFSET + 0x##reg)
0160 #define nv_load_tv_enc(dev, state, reg) \
0161     nv_write_tv_enc(dev, 0x##reg, state->tv_enc[0x##reg])
0162
0163 #endif