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0001 /*
0002  * Copyright 2006 Dave Airlie
0003  * Copyright 2007 Maarten Maathuis
0004  * Copyright 2007-2009 Stuart Bennett
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0020  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
0021  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0022  * SOFTWARE.
0023  */
0024 
0025 #include "nouveau_drv.h"
0026 #include "hw.h"
0027 
0028 #include <subdev/bios/pll.h>
0029 #include <nvif/timer.h>
0030 
0031 #define CHIPSET_NFORCE 0x01a0
0032 #define CHIPSET_NFORCE2 0x01f0
0033 
0034 /*
0035  * misc hw access wrappers/control functions
0036  */
0037 
0038 void
0039 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
0040 {
0041     NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
0042     NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
0043 }
0044 
0045 uint8_t
0046 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
0047 {
0048     NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
0049     return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
0050 }
0051 
0052 void
0053 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
0054 {
0055     NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
0056     NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
0057 }
0058 
0059 uint8_t
0060 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
0061 {
0062     NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
0063     return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
0064 }
0065 
0066 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
0067  * it affects only the 8 bit vga io regs, which we access using mmio at
0068  * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
0069  * in general, the set value of cr44 does not matter: reg access works as
0070  * expected and values can be set for the appropriate head by using a 0x2000
0071  * offset as required
0072  * however:
0073  * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
0074  *    cr44 must be set to 0 or 3 for accessing values on the correct head
0075  *    through the common 0xc03c* addresses
0076  * b) in tied mode (4) head B is programmed to the values set on head A, and
0077  *    access using the head B addresses can have strange results, ergo we leave
0078  *    tied mode in init once we know to what cr44 should be restored on exit
0079  *
0080  * the owner parameter is slightly abused:
0081  * 0 and 1 are treated as head values and so the set value is (owner * 3)
0082  * other values are treated as literal values to set
0083  */
0084 void
0085 NVSetOwner(struct drm_device *dev, int owner)
0086 {
0087     struct nouveau_drm *drm = nouveau_drm(dev);
0088 
0089     if (owner == 1)
0090         owner *= 3;
0091 
0092     if (drm->client.device.info.chipset == 0x11) {
0093         /* This might seem stupid, but the blob does it and
0094          * omitting it often locks the system up.
0095          */
0096         NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
0097         NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
0098     }
0099 
0100     /* CR44 is always changed on CRTC0 */
0101     NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
0102 
0103     if (drm->client.device.info.chipset == 0x11) {  /* set me harder */
0104         NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
0105         NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
0106     }
0107 }
0108 
0109 void
0110 NVBlankScreen(struct drm_device *dev, int head, bool blank)
0111 {
0112     unsigned char seq1;
0113 
0114     if (nv_two_heads(dev))
0115         NVSetOwner(dev, head);
0116 
0117     seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
0118 
0119     NVVgaSeqReset(dev, head, true);
0120     if (blank)
0121         NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
0122     else
0123         NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
0124     NVVgaSeqReset(dev, head, false);
0125 }
0126 
0127 /*
0128  * PLL getting
0129  */
0130 
0131 static void
0132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
0133               uint32_t pll2, struct nvkm_pll_vals *pllvals)
0134 {
0135     struct nouveau_drm *drm = nouveau_drm(dev);
0136 
0137     /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
0138 
0139     /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
0140     pllvals->log2P = (pll1 >> 16) & 0x7;
0141     pllvals->N2 = pllvals->M2 = 1;
0142 
0143     if (reg1 <= 0x405c) {
0144         pllvals->NM1 = pll2 & 0xffff;
0145         /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
0146         if (!(pll1 & 0x1100))
0147             pllvals->NM2 = pll2 >> 16;
0148     } else {
0149         pllvals->NM1 = pll1 & 0xffff;
0150         if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
0151             pllvals->NM2 = pll2 & 0xffff;
0152         else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) {
0153             pllvals->M1 &= 0xf; /* only 4 bits */
0154             if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
0155                 pllvals->M2 = (pll1 >> 4) & 0x7;
0156                 pllvals->N2 = ((pll1 >> 21) & 0x18) |
0157                           ((pll1 >> 19) & 0x7);
0158             }
0159         }
0160     }
0161 }
0162 
0163 int
0164 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
0165                struct nvkm_pll_vals *pllvals)
0166 {
0167     struct nouveau_drm *drm = nouveau_drm(dev);
0168     struct nvif_object *device = &drm->client.device.object;
0169     struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
0170     uint32_t reg1, pll1, pll2 = 0;
0171     struct nvbios_pll pll_lim;
0172     int ret;
0173 
0174     ret = nvbios_pll_parse(bios, plltype, &pll_lim);
0175     if (ret || !(reg1 = pll_lim.reg))
0176         return -ENOENT;
0177 
0178     pll1 = nvif_rd32(device, reg1);
0179     if (reg1 <= 0x405c)
0180         pll2 = nvif_rd32(device, reg1 + 4);
0181     else if (nv_two_reg_pll(dev)) {
0182         uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
0183 
0184         pll2 = nvif_rd32(device, reg2);
0185     }
0186 
0187     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
0188         uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
0189 
0190         /* check whether vpll has been forced into single stage mode */
0191         if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
0192             if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
0193                 pll2 = 0;
0194         } else
0195             if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
0196                 pll2 = 0;
0197     }
0198 
0199     nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
0200     pllvals->refclk = pll_lim.refclk;
0201     return 0;
0202 }
0203 
0204 int
0205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv)
0206 {
0207     /* Avoid divide by zero if called at an inappropriate time */
0208     if (!pv->M1 || !pv->M2)
0209         return 0;
0210 
0211     return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
0212 }
0213 
0214 int
0215 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
0216 {
0217     struct pci_dev *pdev = to_pci_dev(dev->dev);
0218     struct nvkm_pll_vals pllvals;
0219     int ret;
0220     int domain;
0221 
0222     domain = pci_domain_nr(pdev->bus);
0223 
0224     if (plltype == PLL_MEMORY &&
0225         (pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
0226         uint32_t mpllP;
0227         pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
0228                       0x6c, &mpllP);
0229         mpllP = (mpllP >> 8) & 0xf;
0230         if (!mpllP)
0231             mpllP = 4;
0232 
0233         return 400000 / mpllP;
0234     } else
0235     if (plltype == PLL_MEMORY &&
0236         (pdev->device & 0xff0) == CHIPSET_NFORCE2) {
0237         uint32_t clock;
0238 
0239         pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
0240                       0x4c, &clock);
0241         return clock / 1000;
0242     }
0243 
0244     ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
0245     if (ret)
0246         return ret;
0247 
0248     return nouveau_hw_pllvals_to_clk(&pllvals);
0249 }
0250 
0251 static void
0252 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
0253 {
0254     /* the vpll on an unused head can come up with a random value, way
0255      * beyond the pll limits.  for some reason this causes the chip to
0256      * lock up when reading the dac palette regs, so set a valid pll here
0257      * when such a condition detected.  only seen on nv11 to date
0258      */
0259 
0260     struct nouveau_drm *drm = nouveau_drm(dev);
0261     struct nvif_device *device = &drm->client.device;
0262     struct nvkm_clk *clk = nvxx_clk(device);
0263     struct nvkm_bios *bios = nvxx_bios(device);
0264     struct nvbios_pll pll_lim;
0265     struct nvkm_pll_vals pv;
0266     enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
0267 
0268     if (nvbios_pll_parse(bios, pll, &pll_lim))
0269         return;
0270     nouveau_hw_get_pllvals(dev, pll, &pv);
0271 
0272     if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
0273         pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
0274         pv.log2P <= pll_lim.max_p)
0275         return;
0276 
0277     NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1);
0278 
0279     /* set lowest clock within static limits */
0280     pv.M1 = pll_lim.vco1.max_m;
0281     pv.N1 = pll_lim.vco1.min_n;
0282     pv.log2P = pll_lim.max_p_usable;
0283     clk->pll_prog(clk, pll_lim.reg, &pv);
0284 }
0285 
0286 /*
0287  * vga font save/restore
0288  */
0289 
0290 static void nouveau_vga_font_io(struct drm_device *dev,
0291                 void __iomem *iovram,
0292                 bool save, unsigned plane)
0293 {
0294     unsigned i;
0295 
0296     NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
0297     NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
0298     for (i = 0; i < 16384; i++) {
0299         if (save) {
0300             nv04_display(dev)->saved_vga_font[plane][i] =
0301                     ioread32_native(iovram + i * 4);
0302         } else {
0303             iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
0304                             iovram + i * 4);
0305         }
0306     }
0307 }
0308 
0309 void
0310 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
0311 {
0312     struct nouveau_drm *drm = nouveau_drm(dev);
0313     struct pci_dev *pdev = to_pci_dev(dev->dev);
0314     uint8_t misc, gr4, gr5, gr6, seq2, seq4;
0315     bool graphicsmode;
0316     unsigned plane;
0317     void __iomem *iovram;
0318 
0319     if (nv_two_heads(dev))
0320         NVSetOwner(dev, 0);
0321 
0322     NVSetEnablePalette(dev, 0, true);
0323     graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
0324     NVSetEnablePalette(dev, 0, false);
0325 
0326     if (graphicsmode) /* graphics mode => framebuffer => no need to save */
0327         return;
0328 
0329     NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor");
0330 
0331     /* map first 64KiB of VRAM, holds VGA fonts etc */
0332     iovram = ioremap(pci_resource_start(pdev, 1), 65536);
0333     if (!iovram) {
0334         NV_ERROR(drm, "Failed to map VRAM, "
0335                     "cannot save/restore VGA fonts.\n");
0336         return;
0337     }
0338 
0339     if (nv_two_heads(dev))
0340         NVBlankScreen(dev, 1, true);
0341     NVBlankScreen(dev, 0, true);
0342 
0343     /* save control regs */
0344     misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
0345     seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
0346     seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
0347     gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
0348     gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
0349     gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
0350 
0351     NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
0352     NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
0353     NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
0354     NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
0355 
0356     /* store font in planes 0..3 */
0357     for (plane = 0; plane < 4; plane++)
0358         nouveau_vga_font_io(dev, iovram, save, plane);
0359 
0360     /* restore control regs */
0361     NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
0362     NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
0363     NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
0364     NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
0365     NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
0366     NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
0367 
0368     if (nv_two_heads(dev))
0369         NVBlankScreen(dev, 1, false);
0370     NVBlankScreen(dev, 0, false);
0371 
0372     iounmap(iovram);
0373 }
0374 
0375 /*
0376  * mode state save/load
0377  */
0378 
0379 static void
0380 rd_cio_state(struct drm_device *dev, int head,
0381          struct nv04_crtc_reg *crtcstate, int index)
0382 {
0383     crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
0384 }
0385 
0386 static void
0387 wr_cio_state(struct drm_device *dev, int head,
0388          struct nv04_crtc_reg *crtcstate, int index)
0389 {
0390     NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
0391 }
0392 
0393 static void
0394 nv_save_state_ramdac(struct drm_device *dev, int head,
0395              struct nv04_mode_state *state)
0396 {
0397     struct nouveau_drm *drm = nouveau_drm(dev);
0398     struct nv04_crtc_reg *regp = &state->crtc_reg[head];
0399     int i;
0400 
0401     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
0402         regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
0403 
0404     nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
0405     state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
0406     if (nv_two_heads(dev))
0407         state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
0408     if (drm->client.device.info.chipset == 0x11)
0409         regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
0410 
0411     regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
0412 
0413     if (nv_gf4_disp_arch(dev))
0414         regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
0415     if (drm->client.device.info.chipset >= 0x30)
0416         regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
0417 
0418     regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
0419     regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
0420     regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
0421     regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
0422     regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
0423     regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
0424     regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
0425     regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
0426 
0427     for (i = 0; i < 7; i++) {
0428         uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
0429         regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
0430         regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
0431     }
0432 
0433     if (nv_gf4_disp_arch(dev)) {
0434         regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
0435         for (i = 0; i < 3; i++) {
0436             regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
0437             regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
0438         }
0439     }
0440 
0441     regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
0442     regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
0443     if (!nv_gf4_disp_arch(dev) && head == 0) {
0444         /* early chips don't allow access to PRAMDAC_TMDS_* without
0445          * the head A FPCLK on (nv11 even locks up) */
0446         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
0447                   ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
0448     }
0449     regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
0450     regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
0451 
0452     regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
0453 
0454     if (nv_gf4_disp_arch(dev))
0455         regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
0456 
0457     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
0458         regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
0459         regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
0460         regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
0461 
0462         for (i = 0; i < 38; i++)
0463             regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
0464                              NV_PRAMDAC_CTV + 4*i);
0465     }
0466 }
0467 
0468 static void
0469 nv_load_state_ramdac(struct drm_device *dev, int head,
0470              struct nv04_mode_state *state)
0471 {
0472     struct nouveau_drm *drm = nouveau_drm(dev);
0473     struct nvkm_clk *clk = nvxx_clk(&drm->client.device);
0474     struct nv04_crtc_reg *regp = &state->crtc_reg[head];
0475     uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
0476     int i;
0477 
0478     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
0479         NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
0480 
0481     clk->pll_prog(clk, pllreg, &regp->pllvals);
0482     NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
0483     if (nv_two_heads(dev))
0484         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
0485     if (drm->client.device.info.chipset == 0x11)
0486         NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
0487 
0488     NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
0489 
0490     if (nv_gf4_disp_arch(dev))
0491         NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
0492     if (drm->client.device.info.chipset >= 0x30)
0493         NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
0494 
0495     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
0496     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
0497     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
0498     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
0499     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
0500     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
0501     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
0502     NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
0503 
0504     for (i = 0; i < 7; i++) {
0505         uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
0506 
0507         NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
0508         NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
0509     }
0510 
0511     if (nv_gf4_disp_arch(dev)) {
0512         NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
0513         for (i = 0; i < 3; i++) {
0514             NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
0515             NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
0516         }
0517     }
0518 
0519     NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
0520     NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
0521     NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
0522     NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
0523 
0524     NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
0525 
0526     if (nv_gf4_disp_arch(dev))
0527         NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
0528 
0529     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
0530         NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
0531         NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
0532         NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
0533 
0534         for (i = 0; i < 38; i++)
0535             NVWriteRAMDAC(dev, head,
0536                       NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
0537     }
0538 }
0539 
0540 static void
0541 nv_save_state_vga(struct drm_device *dev, int head,
0542           struct nv04_mode_state *state)
0543 {
0544     struct nv04_crtc_reg *regp = &state->crtc_reg[head];
0545     int i;
0546 
0547     regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
0548 
0549     for (i = 0; i < 25; i++)
0550         rd_cio_state(dev, head, regp, i);
0551 
0552     NVSetEnablePalette(dev, head, true);
0553     for (i = 0; i < 21; i++)
0554         regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
0555     NVSetEnablePalette(dev, head, false);
0556 
0557     for (i = 0; i < 9; i++)
0558         regp->Graphics[i] = NVReadVgaGr(dev, head, i);
0559 
0560     for (i = 0; i < 5; i++)
0561         regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
0562 }
0563 
0564 static void
0565 nv_load_state_vga(struct drm_device *dev, int head,
0566           struct nv04_mode_state *state)
0567 {
0568     struct nv04_crtc_reg *regp = &state->crtc_reg[head];
0569     int i;
0570 
0571     NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
0572 
0573     for (i = 0; i < 5; i++)
0574         NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
0575 
0576     nv_lock_vga_crtc_base(dev, head, false);
0577     for (i = 0; i < 25; i++)
0578         wr_cio_state(dev, head, regp, i);
0579     nv_lock_vga_crtc_base(dev, head, true);
0580 
0581     for (i = 0; i < 9; i++)
0582         NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
0583 
0584     NVSetEnablePalette(dev, head, true);
0585     for (i = 0; i < 21; i++)
0586         NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
0587     NVSetEnablePalette(dev, head, false);
0588 }
0589 
0590 static void
0591 nv_save_state_ext(struct drm_device *dev, int head,
0592           struct nv04_mode_state *state)
0593 {
0594     struct nouveau_drm *drm = nouveau_drm(dev);
0595     struct nv04_crtc_reg *regp = &state->crtc_reg[head];
0596     int i;
0597 
0598     rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
0599     rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
0600     rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
0601     rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
0602     rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
0603     rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
0604     rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
0605 
0606     rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
0607     rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
0608     rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
0609 
0610     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
0611         rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
0612 
0613     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
0614         rd_cio_state(dev, head, regp, 0x9f);
0615 
0616     rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
0617     rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
0618     rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
0619     rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
0620     rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
0621 
0622     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
0623         regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
0624         regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
0625 
0626         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
0627             regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
0628 
0629         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
0630             regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
0631 
0632         if (nv_two_heads(dev))
0633             regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
0634         regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
0635     }
0636 
0637     regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
0638 
0639     rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
0640     rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
0641     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
0642         rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
0643         rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
0644         rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
0645         rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
0646     }
0647     /* NV11 and NV20 don't have this, they stop at 0x52. */
0648     if (nv_gf4_disp_arch(dev)) {
0649         rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
0650         rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
0651         rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
0652 
0653         for (i = 0; i < 0x10; i++)
0654             regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
0655         rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
0656         rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
0657 
0658         rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
0659         rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
0660     }
0661 
0662     regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
0663 }
0664 
0665 static void
0666 nv_load_state_ext(struct drm_device *dev, int head,
0667           struct nv04_mode_state *state)
0668 {
0669     struct nouveau_drm *drm = nouveau_drm(dev);
0670     struct nvif_object *device = &drm->client.device.object;
0671     struct nv04_crtc_reg *regp = &state->crtc_reg[head];
0672     uint32_t reg900;
0673     int i;
0674 
0675     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
0676         if (nv_two_heads(dev))
0677             /* setting ENGINE_CTRL (EC) *must* come before
0678              * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
0679              * EC that should not be overwritten by writing stale EC
0680              */
0681             NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
0682 
0683         nvif_wr32(device, NV_PVIDEO_STOP, 1);
0684         nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
0685         nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
0686         nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
0687         nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1);
0688         nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1);
0689         nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1);
0690         nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1);
0691         nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
0692 
0693         NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
0694         NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
0695         NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
0696 
0697         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
0698             NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
0699 
0700         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
0701             NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
0702 
0703             reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
0704             if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
0705                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
0706             else
0707                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
0708         }
0709     }
0710 
0711     NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
0712 
0713     wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
0714     wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
0715     wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
0716     wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
0717     wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
0718     wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
0719     wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
0720     wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
0721     wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
0722 
0723     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
0724         wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
0725 
0726     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
0727         wr_cio_state(dev, head, regp, 0x9f);
0728 
0729     wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
0730     wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
0731     wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
0732     wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
0733     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
0734         nv_fix_nv40_hw_cursor(dev, head);
0735     wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
0736 
0737     wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
0738     wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
0739     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
0740         wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
0741         wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
0742         wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
0743         wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
0744     }
0745     /* NV11 and NV20 stop at 0x52. */
0746     if (nv_gf4_disp_arch(dev)) {
0747         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
0748             /* Not waiting for vertical retrace before modifying
0749                CRE_53/CRE_54 causes lockups. */
0750             nvif_msec(&drm->client.device, 650,
0751                 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
0752                     break;
0753             );
0754             nvif_msec(&drm->client.device, 650,
0755                 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
0756                     break;
0757             );
0758         }
0759 
0760         wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
0761         wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
0762         wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
0763 
0764         for (i = 0; i < 0x10; i++)
0765             NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
0766         wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
0767         wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
0768 
0769         wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
0770         wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
0771     }
0772 
0773     NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
0774 }
0775 
0776 static void
0777 nv_save_state_palette(struct drm_device *dev, int head,
0778               struct nv04_mode_state *state)
0779 {
0780     struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
0781     int head_offset = head * NV_PRMDIO_SIZE, i;
0782 
0783     nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
0784                 NV_PRMDIO_PIXEL_MASK_MASK);
0785     nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
0786 
0787     for (i = 0; i < 768; i++) {
0788         state->crtc_reg[head].DAC[i] = nvif_rd08(device,
0789                 NV_PRMDIO_PALETTE_DATA + head_offset);
0790     }
0791 
0792     NVSetEnablePalette(dev, head, false);
0793 }
0794 
0795 void
0796 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
0797                   struct nv04_mode_state *state)
0798 {
0799     struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
0800     int head_offset = head * NV_PRMDIO_SIZE, i;
0801 
0802     nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
0803                 NV_PRMDIO_PIXEL_MASK_MASK);
0804     nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
0805 
0806     for (i = 0; i < 768; i++) {
0807         nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
0808                 state->crtc_reg[head].DAC[i]);
0809     }
0810 
0811     NVSetEnablePalette(dev, head, false);
0812 }
0813 
0814 void nouveau_hw_save_state(struct drm_device *dev, int head,
0815                struct nv04_mode_state *state)
0816 {
0817     struct nouveau_drm *drm = nouveau_drm(dev);
0818 
0819     if (drm->client.device.info.chipset == 0x11)
0820         /* NB: no attempt is made to restore the bad pll later on */
0821         nouveau_hw_fix_bad_vpll(dev, head);
0822     nv_save_state_ramdac(dev, head, state);
0823     nv_save_state_vga(dev, head, state);
0824     nv_save_state_palette(dev, head, state);
0825     nv_save_state_ext(dev, head, state);
0826 }
0827 
0828 void nouveau_hw_load_state(struct drm_device *dev, int head,
0829                struct nv04_mode_state *state)
0830 {
0831     NVVgaProtect(dev, head, true);
0832     nv_load_state_ramdac(dev, head, state);
0833     nv_load_state_ext(dev, head, state);
0834     nouveau_hw_load_state_palette(dev, head, state);
0835     nv_load_state_vga(dev, head, state);
0836     NVVgaProtect(dev, head, false);
0837 }
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