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0001 /*
0002  * Copyright 2003 NVIDIA, Corporation
0003  * Copyright 2006 Dave Airlie
0004  * Copyright 2007 Maarten Maathuis
0005  * Copyright 2007-2009 Stuart Bennett
0006  *
0007  * Permission is hereby granted, free of charge, to any person obtaining a
0008  * copy of this software and associated documentation files (the "Software"),
0009  * to deal in the Software without restriction, including without limitation
0010  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0011  * and/or sell copies of the Software, and to permit persons to whom the
0012  * Software is furnished to do so, subject to the following conditions:
0013  *
0014  * The above copyright notice and this permission notice (including the next
0015  * paragraph) shall be included in all copies or substantial portions of the
0016  * Software.
0017  *
0018  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0019  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0020  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0021  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0022  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0023  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0024  * DEALINGS IN THE SOFTWARE.
0025  */
0026 
0027 #include <drm/drm_crtc_helper.h>
0028 #include <drm/drm_fourcc.h>
0029 
0030 #include "nouveau_drv.h"
0031 #include "nouveau_reg.h"
0032 #include "nouveau_encoder.h"
0033 #include "nouveau_connector.h"
0034 #include "nouveau_crtc.h"
0035 #include "hw.h"
0036 #include "nvreg.h"
0037 
0038 #include <drm/i2c/sil164.h>
0039 
0040 #include <subdev/i2c.h>
0041 
0042 #define FP_TG_CONTROL_ON  (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |    \
0043                NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |     \
0044                NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
0045 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE |    \
0046                NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
0047                NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
0048 
0049 static inline bool is_fpc_off(uint32_t fpc)
0050 {
0051     return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
0052             FP_TG_CONTROL_OFF);
0053 }
0054 
0055 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
0056 {
0057     /* special case of nv_read_tmds to find crtc associated with an output.
0058      * this does not give a correct answer for off-chip dvi, but there's no
0059      * use for such an answer anyway
0060      */
0061     int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
0062 
0063     NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
0064     NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
0065     return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
0066 }
0067 
0068 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
0069             int head, bool dl)
0070 {
0071     /* The BIOS scripts don't do this for us, sadly
0072      * Luckily we do know the values ;-)
0073      *
0074      * head < 0 indicates we wish to force a setting with the overrideval
0075      * (for VT restore etc.)
0076      */
0077 
0078     int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
0079     uint8_t tmds04 = 0x80;
0080 
0081     if (head != ramdac)
0082         tmds04 = 0x88;
0083 
0084     if (dcbent->type == DCB_OUTPUT_LVDS)
0085         tmds04 |= 0x01;
0086 
0087     nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
0088 
0089     if (dl) /* dual link */
0090         nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
0091 }
0092 
0093 void nv04_dfp_disable(struct drm_device *dev, int head)
0094 {
0095     struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
0096 
0097     if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
0098         FP_TG_CONTROL_ON) {
0099         /* digital remnants must be cleaned before new crtc
0100          * values programmed.  delay is time for the vga stuff
0101          * to realise it's in control again
0102          */
0103         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
0104                   FP_TG_CONTROL_OFF);
0105         msleep(50);
0106     }
0107     /* don't inadvertently turn it on when state written later */
0108     crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
0109     crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
0110         ~NV_CIO_CRE_LCD_ROUTE_MASK;
0111 }
0112 
0113 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
0114 {
0115     struct drm_device *dev = encoder->dev;
0116     struct drm_crtc *crtc;
0117     struct nouveau_crtc *nv_crtc;
0118     uint32_t *fpc;
0119 
0120     if (mode == DRM_MODE_DPMS_ON) {
0121         nv_crtc = nouveau_crtc(encoder->crtc);
0122         fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
0123 
0124         if (is_fpc_off(*fpc)) {
0125             /* using saved value is ok, as (is_digital && dpms_on &&
0126              * fp_control==OFF) is (at present) *only* true when
0127              * fpc's most recent change was by below "off" code
0128              */
0129             *fpc = nv_crtc->dpms_saved_fp_control;
0130         }
0131 
0132         nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
0133         NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
0134     } else {
0135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0136             nv_crtc = nouveau_crtc(crtc);
0137             fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
0138 
0139             nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
0140             if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
0141                 nv_crtc->dpms_saved_fp_control = *fpc;
0142                 /* cut the FP output */
0143                 *fpc &= ~FP_TG_CONTROL_ON;
0144                 *fpc |= FP_TG_CONTROL_OFF;
0145                 NVWriteRAMDAC(dev, nv_crtc->index,
0146                           NV_PRAMDAC_FP_TG_CONTROL, *fpc);
0147             }
0148         }
0149     }
0150 }
0151 
0152 static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
0153 {
0154     struct drm_device *dev = encoder->dev;
0155     struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
0156     struct drm_encoder *slave;
0157 
0158     if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
0159         return NULL;
0160 
0161     /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
0162      * TMDS transmitters at the same I2C address, in the same I2C
0163      * bus. This can still work because in that case one of them is
0164      * always hard-wired to a reasonable configuration using straps,
0165      * and the other one needs to be programmed.
0166      *
0167      * I don't think there's a way to know which is which, even the
0168      * blob programs the one exposed via I2C for *both* heads, so
0169      * let's do the same.
0170      */
0171     list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
0172         struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
0173 
0174         if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
0175             slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
0176             return slave;
0177     }
0178 
0179     return NULL;
0180 }
0181 
0182 static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
0183                 const struct drm_display_mode *mode,
0184                 struct drm_display_mode *adjusted_mode)
0185 {
0186     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0187     struct nouveau_connector *nv_connector =
0188         nv04_encoder_get_connector(nv_encoder);
0189 
0190     if (!nv_connector->native_mode ||
0191         nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
0192         mode->hdisplay > nv_connector->native_mode->hdisplay ||
0193         mode->vdisplay > nv_connector->native_mode->vdisplay) {
0194         nv_encoder->mode = *adjusted_mode;
0195 
0196     } else {
0197         nv_encoder->mode = *nv_connector->native_mode;
0198         adjusted_mode->clock = nv_connector->native_mode->clock;
0199     }
0200 
0201     return true;
0202 }
0203 
0204 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
0205                      struct nouveau_encoder *nv_encoder, int head)
0206 {
0207     struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
0208     uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
0209 
0210     if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
0211         return;
0212 
0213     /* SEL_CLK is only used on the primary ramdac
0214      * It toggles spread spectrum PLL output and sets the bindings of PLLs
0215      * to heads on digital outputs
0216      */
0217     if (head)
0218         state->sel_clk |= bits1618;
0219     else
0220         state->sel_clk &= ~bits1618;
0221 
0222     /* nv30:
0223      *  bit 0       NVClk spread spectrum on/off
0224      *  bit 2       MemClk spread spectrum on/off
0225      *  bit 4       PixClk1 spread spectrum on/off toggle
0226      *  bit 6       PixClk2 spread spectrum on/off toggle
0227      *
0228      * nv40 (observations from bios behaviour and mmio traces):
0229      *  bits 4&6    as for nv30
0230      *  bits 5&7    head dependent as for bits 4&6, but do not appear with 4&6;
0231      *          maybe a different spread mode
0232      *  bits 8&10   seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
0233      *  The logic behind turning spread spectrum on/off in the first place,
0234      *  and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
0235      *  entry has the necessary info)
0236      */
0237     if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
0238         int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
0239 
0240         state->sel_clk &= ~0xf0;
0241         state->sel_clk |= (head ? 0x40 : 0x10) << shift;
0242     }
0243 }
0244 
0245 static void nv04_dfp_prepare(struct drm_encoder *encoder)
0246 {
0247     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0248     const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
0249     struct drm_device *dev = encoder->dev;
0250     int head = nouveau_crtc(encoder->crtc)->index;
0251     struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
0252     uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
0253     uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
0254 
0255     helper->dpms(encoder, DRM_MODE_DPMS_OFF);
0256 
0257     nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
0258 
0259     *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
0260 
0261     if (nv_two_heads(dev)) {
0262         if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
0263             *cr_lcd |= head ? 0x0 : 0x8;
0264         else {
0265             *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
0266             if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
0267                 *cr_lcd |= 0x30;
0268             if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
0269                 /* avoid being connected to both crtcs */
0270                 *cr_lcd_oth &= ~0x30;
0271                 NVWriteVgaCrtc(dev, head ^ 1,
0272                            NV_CIO_CRE_LCD__INDEX,
0273                            *cr_lcd_oth);
0274             }
0275         }
0276     }
0277 }
0278 
0279 
0280 static void nv04_dfp_mode_set(struct drm_encoder *encoder,
0281                   struct drm_display_mode *mode,
0282                   struct drm_display_mode *adjusted_mode)
0283 {
0284     struct drm_device *dev = encoder->dev;
0285     struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
0286     struct nouveau_drm *drm = nouveau_drm(dev);
0287     struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
0288     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0289     struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
0290     struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
0291     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0292     struct drm_display_mode *output_mode = &nv_encoder->mode;
0293     struct drm_connector *connector = &nv_connector->base;
0294     const struct drm_framebuffer *fb = encoder->crtc->primary->fb;
0295     uint32_t mode_ratio, panel_ratio;
0296 
0297     NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
0298     drm_mode_debug_printmodeline(output_mode);
0299 
0300     /* Initialize the FP registers in this CRTC. */
0301     regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
0302     regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
0303     if (!nv_gf4_disp_arch(dev) ||
0304         (output_mode->hsync_start - output_mode->hdisplay) >=
0305                     drm->vbios.digital_min_front_porch)
0306         regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
0307     else
0308         regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
0309     regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
0310     regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
0311     regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
0312     regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
0313 
0314     regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
0315     regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
0316     regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
0317     regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
0318     regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
0319     regp->fp_vert_regs[FP_VALID_START] = 0;
0320     regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
0321 
0322     /* bit26: a bit seen on some g7x, no as yet discernable purpose */
0323     regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
0324                (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
0325     /* Deal with vsync/hsync polarity */
0326     /* LVDS screens do set this, but modes with +ve syncs are very rare */
0327     if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
0328         regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
0329     if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
0330         regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
0331     /* panel scaling first, as native would get set otherwise */
0332     if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
0333         nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER)    /* panel handles it */
0334         regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
0335     else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
0336          adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
0337         regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
0338     else /* gpu needs to scale */
0339         regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
0340     if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
0341         regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
0342     if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
0343         output_mode->clock > 165000)
0344         regp->fp_control |= (2 << 24);
0345     if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
0346         bool duallink = false, dummy;
0347         if (nv_connector->edid &&
0348             nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
0349             duallink = (((u8 *)nv_connector->edid)[121] == 2);
0350         } else {
0351             nouveau_bios_parse_lvds_table(dev, output_mode->clock,
0352                               &duallink, &dummy);
0353         }
0354 
0355         if (duallink)
0356             regp->fp_control |= (8 << 28);
0357     } else
0358     if (output_mode->clock > 165000)
0359         regp->fp_control |= (8 << 28);
0360 
0361     regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
0362                NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
0363                NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
0364                NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
0365                NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
0366                NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
0367                NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
0368 
0369     /* We want automatic scaling */
0370     regp->fp_debug_1 = 0;
0371     /* This can override HTOTAL and VTOTAL */
0372     regp->fp_debug_2 = 0;
0373 
0374     /* Use 20.12 fixed point format to avoid floats */
0375     mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
0376     panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
0377     /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
0378      * get treated the same as SCALE_FULLSCREEN */
0379     if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
0380         mode_ratio != panel_ratio) {
0381         uint32_t diff, scale;
0382         bool divide_by_2 = nv_gf4_disp_arch(dev);
0383 
0384         if (mode_ratio < panel_ratio) {
0385             /* vertical needs to expand to glass size (automatic)
0386              * horizontal needs to be scaled at vertical scale factor
0387              * to maintain aspect */
0388 
0389             scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
0390             regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
0391                        XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
0392 
0393             /* restrict area of screen used, horizontally */
0394             diff = output_mode->hdisplay -
0395                    output_mode->vdisplay * mode_ratio / (1 << 12);
0396             regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
0397             regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
0398         }
0399 
0400         if (mode_ratio > panel_ratio) {
0401             /* horizontal needs to expand to glass size (automatic)
0402              * vertical needs to be scaled at horizontal scale factor
0403              * to maintain aspect */
0404 
0405             scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
0406             regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
0407                        XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
0408 
0409             /* restrict area of screen used, vertically */
0410             diff = output_mode->vdisplay -
0411                    (1 << 12) * output_mode->hdisplay / mode_ratio;
0412             regp->fp_vert_regs[FP_VALID_START] += diff / 2;
0413             regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
0414         }
0415     }
0416 
0417     /* Output property. */
0418     if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
0419         (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
0420          fb->format->depth > connector->display_info.bpc * 3)) {
0421         if (drm->client.device.info.chipset == 0x11)
0422             regp->dither = savep->dither | 0x00010000;
0423         else {
0424             int i;
0425             regp->dither = savep->dither | 0x00000001;
0426             for (i = 0; i < 3; i++) {
0427                 regp->dither_regs[i] = 0xe4e4e4e4;
0428                 regp->dither_regs[i + 3] = 0x44444444;
0429             }
0430         }
0431     } else {
0432         if (drm->client.device.info.chipset != 0x11) {
0433             /* reset them */
0434             int i;
0435             for (i = 0; i < 3; i++) {
0436                 regp->dither_regs[i] = savep->dither_regs[i];
0437                 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
0438             }
0439         }
0440         regp->dither = savep->dither;
0441     }
0442 
0443     regp->fp_margin_color = 0;
0444 }
0445 
0446 static void nv04_dfp_commit(struct drm_encoder *encoder)
0447 {
0448     struct drm_device *dev = encoder->dev;
0449     struct nouveau_drm *drm = nouveau_drm(dev);
0450     const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
0451     struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
0452     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0453     struct dcb_output *dcbe = nv_encoder->dcb;
0454     int head = nouveau_crtc(encoder->crtc)->index;
0455     struct drm_encoder *slave_encoder;
0456 
0457     if (dcbe->type == DCB_OUTPUT_TMDS)
0458         run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
0459     else if (dcbe->type == DCB_OUTPUT_LVDS)
0460         call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
0461 
0462     /* update fp_control state for any changes made by scripts,
0463      * so correct value is written at DPMS on */
0464     nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
0465         NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
0466 
0467     /* This could use refinement for flatpanels, but it should work this way */
0468     if (drm->client.device.info.chipset < 0x44)
0469         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
0470     else
0471         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
0472 
0473     /* Init external transmitters */
0474     slave_encoder = get_tmds_slave(encoder);
0475     if (slave_encoder)
0476         get_slave_funcs(slave_encoder)->mode_set(
0477             slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
0478 
0479     helper->dpms(encoder, DRM_MODE_DPMS_ON);
0480 
0481     NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n",
0482          nv04_encoder_get_connector(nv_encoder)->base.name,
0483          nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
0484 }
0485 
0486 static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
0487 {
0488 #ifdef __powerpc__
0489     struct drm_device *dev = encoder->dev;
0490     struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
0491     struct pci_dev *pdev = to_pci_dev(dev->dev);
0492 
0493     /* BIOS scripts usually take care of the backlight, thanks
0494      * Apple for your consistency.
0495      */
0496     if (pdev->device == 0x0174 || pdev->device == 0x0179 ||
0497         pdev->device == 0x0189 || pdev->device == 0x0329) {
0498         if (mode == DRM_MODE_DPMS_ON) {
0499             nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
0500             nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
0501         } else {
0502             nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
0503             nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
0504         }
0505     }
0506 #endif
0507 }
0508 
0509 static inline bool is_powersaving_dpms(int mode)
0510 {
0511     return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED;
0512 }
0513 
0514 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
0515 {
0516     struct drm_device *dev = encoder->dev;
0517     struct drm_crtc *crtc = encoder->crtc;
0518     struct nouveau_drm *drm = nouveau_drm(dev);
0519     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0520     bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
0521 
0522     if (nv_encoder->last_dpms == mode)
0523         return;
0524     nv_encoder->last_dpms = mode;
0525 
0526     NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n",
0527          mode, nv_encoder->dcb->index);
0528 
0529     if (was_powersaving && is_powersaving_dpms(mode))
0530         return;
0531 
0532     if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
0533         /* when removing an output, crtc may not be set, but PANEL_OFF
0534          * must still be run
0535          */
0536         int head = crtc ? nouveau_crtc(crtc)->index :
0537                nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
0538 
0539         if (mode == DRM_MODE_DPMS_ON) {
0540             call_lvds_script(dev, nv_encoder->dcb, head,
0541                      LVDS_PANEL_ON, nv_encoder->mode.clock);
0542         } else
0543             /* pxclk of 0 is fine for PANEL_OFF, and for a
0544              * disconnected LVDS encoder there is no native_mode
0545              */
0546             call_lvds_script(dev, nv_encoder->dcb, head,
0547                      LVDS_PANEL_OFF, 0);
0548     }
0549 
0550     nv04_dfp_update_backlight(encoder, mode);
0551     nv04_dfp_update_fp_control(encoder, mode);
0552 
0553     if (mode == DRM_MODE_DPMS_ON)
0554         nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
0555     else {
0556         nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
0557         nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
0558     }
0559     NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
0560 }
0561 
0562 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
0563 {
0564     struct nouveau_drm *drm = nouveau_drm(encoder->dev);
0565     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0566 
0567     if (nv_encoder->last_dpms == mode)
0568         return;
0569     nv_encoder->last_dpms = mode;
0570 
0571     NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n",
0572          mode, nv_encoder->dcb->index);
0573 
0574     nv04_dfp_update_backlight(encoder, mode);
0575     nv04_dfp_update_fp_control(encoder, mode);
0576 }
0577 
0578 static void nv04_dfp_save(struct drm_encoder *encoder)
0579 {
0580     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0581     struct drm_device *dev = encoder->dev;
0582 
0583     if (nv_two_heads(dev))
0584         nv_encoder->restore.head =
0585             nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
0586 }
0587 
0588 static void nv04_dfp_restore(struct drm_encoder *encoder)
0589 {
0590     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0591     struct drm_device *dev = encoder->dev;
0592     int head = nv_encoder->restore.head;
0593 
0594     if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
0595         struct nouveau_connector *connector =
0596             nv04_encoder_get_connector(nv_encoder);
0597 
0598         if (connector && connector->native_mode)
0599             call_lvds_script(dev, nv_encoder->dcb, head,
0600                      LVDS_PANEL_ON,
0601                      connector->native_mode->clock);
0602 
0603     } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
0604         int clock = nouveau_hw_pllvals_to_clk
0605                     (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
0606 
0607         run_tmds_table(dev, nv_encoder->dcb, head, clock);
0608     }
0609 
0610     nv_encoder->last_dpms = NV_DPMS_CLEARED;
0611 }
0612 
0613 static void nv04_dfp_destroy(struct drm_encoder *encoder)
0614 {
0615     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0616 
0617     if (get_slave_funcs(encoder))
0618         get_slave_funcs(encoder)->destroy(encoder);
0619 
0620     drm_encoder_cleanup(encoder);
0621     kfree(nv_encoder);
0622 }
0623 
0624 static void nv04_tmds_slave_init(struct drm_encoder *encoder)
0625 {
0626     struct drm_device *dev = encoder->dev;
0627     struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
0628     struct nouveau_drm *drm = nouveau_drm(dev);
0629     struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
0630     struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI);
0631     struct nvkm_i2c_bus_probe info[] = {
0632         {
0633             {
0634                 .type = "sil164",
0635                 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
0636                 .platform_data = &(struct sil164_encoder_params) {
0637                     SIL164_INPUT_EDGE_RISING
0638                  }
0639             }, 0
0640         },
0641         { }
0642     };
0643     int type;
0644 
0645     if (!nv_gf4_disp_arch(dev) || !bus || get_tmds_slave(encoder))
0646         return;
0647 
0648     type = nvkm_i2c_bus_probe(bus, "TMDS transmitter", info, NULL, NULL);
0649     if (type < 0)
0650         return;
0651 
0652     drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
0653                  &bus->i2c, &info[type].dev);
0654 }
0655 
0656 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
0657     .dpms = nv04_lvds_dpms,
0658     .mode_fixup = nv04_dfp_mode_fixup,
0659     .prepare = nv04_dfp_prepare,
0660     .commit = nv04_dfp_commit,
0661     .mode_set = nv04_dfp_mode_set,
0662     .detect = NULL,
0663 };
0664 
0665 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
0666     .dpms = nv04_tmds_dpms,
0667     .mode_fixup = nv04_dfp_mode_fixup,
0668     .prepare = nv04_dfp_prepare,
0669     .commit = nv04_dfp_commit,
0670     .mode_set = nv04_dfp_mode_set,
0671     .detect = NULL,
0672 };
0673 
0674 static const struct drm_encoder_funcs nv04_dfp_funcs = {
0675     .destroy = nv04_dfp_destroy,
0676 };
0677 
0678 int
0679 nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
0680 {
0681     const struct drm_encoder_helper_funcs *helper;
0682     struct nouveau_encoder *nv_encoder = NULL;
0683     struct drm_encoder *encoder;
0684     int type;
0685 
0686     switch (entry->type) {
0687     case DCB_OUTPUT_TMDS:
0688         type = DRM_MODE_ENCODER_TMDS;
0689         helper = &nv04_tmds_helper_funcs;
0690         break;
0691     case DCB_OUTPUT_LVDS:
0692         type = DRM_MODE_ENCODER_LVDS;
0693         helper = &nv04_lvds_helper_funcs;
0694         break;
0695     default:
0696         return -EINVAL;
0697     }
0698 
0699     nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
0700     if (!nv_encoder)
0701         return -ENOMEM;
0702 
0703     nv_encoder->enc_save = nv04_dfp_save;
0704     nv_encoder->enc_restore = nv04_dfp_restore;
0705 
0706     encoder = to_drm_encoder(nv_encoder);
0707 
0708     nv_encoder->dcb = entry;
0709     nv_encoder->or = ffs(entry->or) - 1;
0710 
0711     drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type, NULL);
0712     drm_encoder_helper_add(encoder, helper);
0713 
0714     encoder->possible_crtcs = entry->heads;
0715     encoder->possible_clones = 0;
0716 
0717     if (entry->type == DCB_OUTPUT_TMDS &&
0718         entry->location != DCB_LOC_ON_CHIP)
0719         nv04_tmds_slave_init(encoder);
0720 
0721     drm_connector_attach_encoder(connector, encoder);
0722     return 0;
0723 }
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