nouveau/dispnv04/cursor.c

0001 // SPDX-License-Identifier: MIT
0002 #include <drm/drm_mode.h>
0003 #include "nouveau_drv.h"
0004 #include "nouveau_reg.h"
0005 #include "nouveau_crtc.h"
0006 #include "hw.h"
0007
0008 static void
0009 nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
0010 {
0011     nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
0012 }
0013
0014 static void
0015 nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
0016 {
0017     nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
0018 }
0019
0020 static void
0021 nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
0022 {
0023     nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
0024     NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
0025               NV_PRAMDAC_CU_START_POS,
0026               XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
0027               XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
0028 }
0029
0030 static void
0031 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
0032 {
0033     NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
0034                crtcstate->CRTC[index]);
0035 }
0036
0037 static void
0038 nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
0039 {
0040     struct drm_device *dev = nv_crtc->base.dev;
0041     struct nouveau_drm *drm = nouveau_drm(dev);
0042     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0043     struct drm_crtc *crtc = &nv_crtc->base;
0044
0045     regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
0046         MASK(NV_CIO_CRE_HCUR_ASI) |
0047         XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
0048     regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
0049         XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
0050     if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
0051         regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
0052             MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
0053     regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
0054
0055     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
0056     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
0057     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
0058     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
0059         nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
0060 }
0061
0062 int
0063 nv04_cursor_init(struct nouveau_crtc *crtc)
0064 {
0065     crtc->cursor.set_offset = nv04_cursor_set_offset;
0066     crtc->cursor.set_pos = nv04_cursor_set_pos;
0067     crtc->cursor.hide = nv04_cursor_hide;
0068     crtc->cursor.show = nv04_cursor_show;
0069     return 0;
0070 }