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0001 /*
0002  * Copyright 1993-2003 NVIDIA, Corporation
0003  * Copyright 2006 Dave Airlie
0004  * Copyright 2007 Maarten Maathuis
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the next
0014  * paragraph) shall be included in all copies or substantial portions of the
0015  * Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0018  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0019  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0020  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0021  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0022  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0023  * DEALINGS IN THE SOFTWARE.
0024  */
0025 #include <drm/drm_crtc_helper.h>
0026 #include <drm/drm_fourcc.h>
0027 #include <drm/drm_plane_helper.h>
0028 #include <drm/drm_vblank.h>
0029 
0030 #include "nouveau_drv.h"
0031 #include "nouveau_reg.h"
0032 #include "nouveau_ttm.h"
0033 #include "nouveau_bo.h"
0034 #include "nouveau_gem.h"
0035 #include "nouveau_encoder.h"
0036 #include "nouveau_connector.h"
0037 #include "nouveau_crtc.h"
0038 #include "hw.h"
0039 #include "nvreg.h"
0040 #include "nouveau_fbcon.h"
0041 #include "disp.h"
0042 #include "nouveau_dma.h"
0043 
0044 #include <subdev/bios/pll.h>
0045 #include <subdev/clk.h>
0046 
0047 #include <nvif/push006c.h>
0048 
0049 #include <nvif/event.h>
0050 #include <nvif/cl0046.h>
0051 
0052 static int
0053 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
0054             struct drm_framebuffer *old_fb);
0055 
0056 static void
0057 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
0058 {
0059     NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
0060                crtcstate->CRTC[index]);
0061 }
0062 
0063 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
0064 {
0065     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0066     struct drm_device *dev = crtc->dev;
0067     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0068 
0069     regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
0070     if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
0071         regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
0072         regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
0073         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
0074     }
0075     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
0076 }
0077 
0078 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
0079 {
0080     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0081     struct drm_device *dev = crtc->dev;
0082     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0083 
0084     nv_crtc->sharpness = level;
0085     if (level < 0)  /* blur is in hw range 0x3f -> 0x20 */
0086         level += 0x40;
0087     regp->ramdac_634 = level;
0088     NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
0089 }
0090 
0091 #define PLLSEL_VPLL1_MASK               \
0092     (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL   \
0093      | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
0094 #define PLLSEL_VPLL2_MASK               \
0095     (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2       \
0096      | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
0097 #define PLLSEL_TV_MASK                  \
0098     (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1      \
0099      | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1     \
0100      | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2    \
0101      | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
0102 
0103 /* NV4x 0x40.. pll notes:
0104  * gpu pll: 0x4000 + 0x4004
0105  * ?gpu? pll: 0x4008 + 0x400c
0106  * vpll1: 0x4010 + 0x4014
0107  * vpll2: 0x4018 + 0x401c
0108  * mpll: 0x4020 + 0x4024
0109  * mpll: 0x4038 + 0x403c
0110  *
0111  * the first register of each pair has some unknown details:
0112  * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
0113  * bits 20-23: (mpll) something to do with post divider?
0114  * bits 28-31: related to single stage mode? (bit 8/12)
0115  */
0116 
0117 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
0118 {
0119     struct drm_device *dev = crtc->dev;
0120     struct nouveau_drm *drm = nouveau_drm(dev);
0121     struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
0122     struct nvkm_clk *clk = nvxx_clk(&drm->client.device);
0123     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0124     struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
0125     struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
0126     struct nvkm_pll_vals *pv = &regp->pllvals;
0127     struct nvbios_pll pll_lim;
0128 
0129     if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
0130                 &pll_lim))
0131         return;
0132 
0133     /* NM2 == 0 is used to determine single stage mode on two stage plls */
0134     pv->NM2 = 0;
0135 
0136     /* for newer nv4x the blob uses only the first stage of the vpll below a
0137      * certain clock.  for a certain nv4b this is 150MHz.  since the max
0138      * output frequency of the first stage for this card is 300MHz, it is
0139      * assumed the threshold is given by vco1 maxfreq/2
0140      */
0141     /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
0142      * not 8, others unknown), the blob always uses both plls.  no problem
0143      * has yet been observed in allowing the use a single stage pll on all
0144      * nv43 however.  the behaviour of single stage use is untested on nv40
0145      */
0146     if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
0147         memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
0148 
0149 
0150     if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
0151         return;
0152 
0153     state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
0154 
0155     /* The blob uses this always, so let's do the same */
0156     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
0157         state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
0158     /* again nv40 and some nv43 act more like nv3x as described above */
0159     if (drm->client.device.info.chipset < 0x41)
0160         state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
0161                  NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
0162     state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
0163 
0164     if (pv->NM2)
0165         NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
0166              pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
0167     else
0168         NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
0169              pv->N1, pv->M1, pv->log2P);
0170 
0171     nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
0172 }
0173 
0174 static void
0175 nv_crtc_dpms(struct drm_crtc *crtc, int mode)
0176 {
0177     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0178     struct drm_device *dev = crtc->dev;
0179     struct nouveau_drm *drm = nouveau_drm(dev);
0180     unsigned char seq1 = 0, crtc17 = 0;
0181     unsigned char crtc1A;
0182 
0183     NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
0184                             nv_crtc->index);
0185 
0186     if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
0187         return;
0188 
0189     nv_crtc->last_dpms = mode;
0190 
0191     if (nv_two_heads(dev))
0192         NVSetOwner(dev, nv_crtc->index);
0193 
0194     /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
0195     crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
0196                     NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
0197     switch (mode) {
0198     case DRM_MODE_DPMS_STANDBY:
0199         /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
0200         seq1 = 0x20;
0201         crtc17 = 0x80;
0202         crtc1A |= 0x80;
0203         break;
0204     case DRM_MODE_DPMS_SUSPEND:
0205         /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
0206         seq1 = 0x20;
0207         crtc17 = 0x80;
0208         crtc1A |= 0x40;
0209         break;
0210     case DRM_MODE_DPMS_OFF:
0211         /* Screen: Off; HSync: Off, VSync: Off */
0212         seq1 = 0x20;
0213         crtc17 = 0x00;
0214         crtc1A |= 0xC0;
0215         break;
0216     case DRM_MODE_DPMS_ON:
0217     default:
0218         /* Screen: On; HSync: On, VSync: On */
0219         seq1 = 0x00;
0220         crtc17 = 0x80;
0221         break;
0222     }
0223 
0224     NVVgaSeqReset(dev, nv_crtc->index, true);
0225     /* Each head has it's own sequencer, so we can turn it off when we want */
0226     seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
0227     NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
0228     crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
0229     mdelay(10);
0230     NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
0231     NVVgaSeqReset(dev, nv_crtc->index, false);
0232 
0233     NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
0234 }
0235 
0236 static void
0237 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
0238 {
0239     struct drm_device *dev = crtc->dev;
0240     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0241     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0242     struct drm_framebuffer *fb = crtc->primary->fb;
0243 
0244     /* Calculate our timings */
0245     int horizDisplay    = (mode->crtc_hdisplay >> 3)        - 1;
0246     int horizStart      = (mode->crtc_hsync_start >> 3)     + 1;
0247     int horizEnd        = (mode->crtc_hsync_end >> 3)       + 1;
0248     int horizTotal      = (mode->crtc_htotal >> 3)      - 5;
0249     int horizBlankStart = (mode->crtc_hdisplay >> 3)        - 1;
0250     int horizBlankEnd   = (mode->crtc_htotal >> 3)      - 1;
0251     int vertDisplay     = mode->crtc_vdisplay           - 1;
0252     int vertStart       = mode->crtc_vsync_start        - 1;
0253     int vertEnd     = mode->crtc_vsync_end          - 1;
0254     int vertTotal       = mode->crtc_vtotal             - 2;
0255     int vertBlankStart  = mode->crtc_vdisplay           - 1;
0256     int vertBlankEnd    = mode->crtc_vtotal         - 1;
0257 
0258     struct drm_encoder *encoder;
0259     bool fp_output = false;
0260 
0261     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
0262         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0263 
0264         if (encoder->crtc == crtc &&
0265             (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
0266              nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
0267             fp_output = true;
0268     }
0269 
0270     if (fp_output) {
0271         vertStart = vertTotal - 3;
0272         vertEnd = vertTotal - 2;
0273         vertBlankStart = vertStart;
0274         horizStart = horizTotal - 5;
0275         horizEnd = horizTotal - 2;
0276         horizBlankEnd = horizTotal + 4;
0277 #if 0
0278         if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
0279             /* This reportedly works around some video overlay bandwidth problems */
0280             horizTotal += 2;
0281 #endif
0282     }
0283 
0284     if (mode->flags & DRM_MODE_FLAG_INTERLACE)
0285         vertTotal |= 1;
0286 
0287 #if 0
0288     ErrorF("horizDisplay: 0x%X \n", horizDisplay);
0289     ErrorF("horizStart: 0x%X \n", horizStart);
0290     ErrorF("horizEnd: 0x%X \n", horizEnd);
0291     ErrorF("horizTotal: 0x%X \n", horizTotal);
0292     ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
0293     ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
0294     ErrorF("vertDisplay: 0x%X \n", vertDisplay);
0295     ErrorF("vertStart: 0x%X \n", vertStart);
0296     ErrorF("vertEnd: 0x%X \n", vertEnd);
0297     ErrorF("vertTotal: 0x%X \n", vertTotal);
0298     ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
0299     ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
0300 #endif
0301 
0302     /*
0303     * compute correct Hsync & Vsync polarity
0304     */
0305     if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
0306         && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
0307 
0308         regp->MiscOutReg = 0x23;
0309         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
0310             regp->MiscOutReg |= 0x40;
0311         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
0312             regp->MiscOutReg |= 0x80;
0313     } else {
0314         int vdisplay = mode->vdisplay;
0315         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
0316             vdisplay *= 2;
0317         if (mode->vscan > 1)
0318             vdisplay *= mode->vscan;
0319         if (vdisplay < 400)
0320             regp->MiscOutReg = 0xA3;    /* +hsync -vsync */
0321         else if (vdisplay < 480)
0322             regp->MiscOutReg = 0x63;    /* -hsync +vsync */
0323         else if (vdisplay < 768)
0324             regp->MiscOutReg = 0xE3;    /* -hsync -vsync */
0325         else
0326             regp->MiscOutReg = 0x23;    /* +hsync +vsync */
0327     }
0328 
0329     /*
0330      * Time Sequencer
0331      */
0332     regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
0333     /* 0x20 disables the sequencer */
0334     if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
0335         regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
0336     else
0337         regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
0338     regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
0339     regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
0340     regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
0341 
0342     /*
0343      * CRTC
0344      */
0345     regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
0346     regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
0347     regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
0348     regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
0349                       XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
0350     regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
0351     regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
0352                       XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
0353     regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
0354     regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
0355                       XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
0356                       XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
0357                       (1 << 4) |
0358                       XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
0359                       XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
0360                       XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
0361                       XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
0362     regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
0363     regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
0364                           1 << 6 |
0365                           XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
0366     regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
0367     regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
0368     regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
0369     regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
0370     regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
0371     regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
0372     regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
0373     regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
0374     regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
0375     /* framebuffer can be larger than crtc scanout area. */
0376     regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
0377     regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
0378     regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
0379     regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
0380     regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
0381     regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
0382 
0383     /*
0384      * Some extended CRTC registers (they are not saved with the rest of the vga regs).
0385      */
0386 
0387     /* framebuffer can be larger than crtc scanout area. */
0388     regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
0389         XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
0390     regp->CRTC[NV_CIO_CRE_42] =
0391         XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
0392     regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
0393                         MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
0394     regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
0395                        XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
0396                        XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
0397                        XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
0398                        XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
0399     regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
0400                         XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
0401                         XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
0402                         XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
0403     regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
0404                        XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
0405                        XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
0406                        XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
0407 
0408     if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
0409         horizTotal = (horizTotal >> 1) & ~1;
0410         regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
0411         regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
0412     } else
0413         regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;  /* interlace off */
0414 
0415     /*
0416     * Graphics Display Controller
0417     */
0418     regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
0419     regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
0420     regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
0421     regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
0422     regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
0423     regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
0424     regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
0425     regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
0426     regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
0427 
0428     regp->Attribute[0]  = 0x00; /* standard colormap translation */
0429     regp->Attribute[1]  = 0x01;
0430     regp->Attribute[2]  = 0x02;
0431     regp->Attribute[3]  = 0x03;
0432     regp->Attribute[4]  = 0x04;
0433     regp->Attribute[5]  = 0x05;
0434     regp->Attribute[6]  = 0x06;
0435     regp->Attribute[7]  = 0x07;
0436     regp->Attribute[8]  = 0x08;
0437     regp->Attribute[9]  = 0x09;
0438     regp->Attribute[10] = 0x0A;
0439     regp->Attribute[11] = 0x0B;
0440     regp->Attribute[12] = 0x0C;
0441     regp->Attribute[13] = 0x0D;
0442     regp->Attribute[14] = 0x0E;
0443     regp->Attribute[15] = 0x0F;
0444     regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
0445     /* Non-vga */
0446     regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
0447     regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
0448     regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
0449     regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
0450 }
0451 
0452 /**
0453  * Sets up registers for the given mode/adjusted_mode pair.
0454  *
0455  * The clocks, CRTCs and outputs attached to this CRTC must be off.
0456  *
0457  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
0458  * be easily turned on/off after this.
0459  */
0460 static void
0461 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
0462 {
0463     struct drm_device *dev = crtc->dev;
0464     struct nouveau_drm *drm = nouveau_drm(dev);
0465     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0466     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0467     struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
0468     const struct drm_framebuffer *fb = crtc->primary->fb;
0469     struct drm_encoder *encoder;
0470     bool lvds_output = false, tmds_output = false, tv_output = false,
0471         off_chip_digital = false;
0472 
0473     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
0474         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0475         bool digital = false;
0476 
0477         if (encoder->crtc != crtc)
0478             continue;
0479 
0480         if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
0481             digital = lvds_output = true;
0482         if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
0483             tv_output = true;
0484         if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
0485             digital = tmds_output = true;
0486         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
0487             off_chip_digital = true;
0488     }
0489 
0490     /* Registers not directly related to the (s)vga mode */
0491 
0492     /* What is the meaning of this register? */
0493     /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
0494     regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
0495 
0496     regp->crtc_eng_ctrl = 0;
0497     /* Except for rare conditions I2C is enabled on the primary crtc */
0498     if (nv_crtc->index == 0)
0499         regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
0500 #if 0
0501     /* Set overlay to desired crtc. */
0502     if (dev->overlayAdaptor) {
0503         NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
0504         if (pPriv->overlayCRTC == nv_crtc->index)
0505             regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
0506     }
0507 #endif
0508 
0509     /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
0510     regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
0511                  NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
0512                  NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
0513     if (drm->client.device.info.chipset >= 0x11)
0514         regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
0515     if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
0516         regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
0517 
0518     /* Unblock some timings */
0519     regp->CRTC[NV_CIO_CRE_53] = 0;
0520     regp->CRTC[NV_CIO_CRE_54] = 0;
0521 
0522     /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
0523     if (lvds_output)
0524         regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
0525     else if (tmds_output)
0526         regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
0527     else
0528         regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
0529 
0530     /* These values seem to vary */
0531     /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
0532     regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
0533 
0534     nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
0535 
0536     /* probably a scratch reg, but kept for cargo-cult purposes:
0537      * bit0: crtc0?, head A
0538      * bit6: lvds, head A
0539      * bit7: (only in X), head A
0540      */
0541     if (nv_crtc->index == 0)
0542         regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
0543 
0544     /* The blob seems to take the current value from crtc 0, add 4 to that
0545      * and reuse the old value for crtc 1 */
0546     regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
0547     if (!nv_crtc->index)
0548         regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
0549 
0550     /* the blob sometimes sets |= 0x10 (which is the same as setting |=
0551      * 1 << 30 on 0x60.830), for no apparent reason */
0552     regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
0553 
0554     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
0555         regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
0556 
0557     regp->crtc_830 = mode->crtc_vdisplay - 3;
0558     regp->crtc_834 = mode->crtc_vdisplay - 1;
0559 
0560     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
0561         /* This is what the blob does */
0562         regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
0563 
0564     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
0565         regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
0566 
0567     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
0568         regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
0569     else
0570         regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
0571 
0572     /* Some misc regs */
0573     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
0574         regp->CRTC[NV_CIO_CRE_85] = 0xFF;
0575         regp->CRTC[NV_CIO_CRE_86] = 0x1;
0576     }
0577 
0578     regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
0579     /* Enable slaved mode (called MODE_TV in nv4ref.h) */
0580     if (lvds_output || tmds_output || tv_output)
0581         regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
0582 
0583     /* Generic PRAMDAC regs */
0584 
0585     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
0586         /* Only bit that bios and blob set. */
0587         regp->nv10_cursync = (1 << 25);
0588 
0589     regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
0590                 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
0591                 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
0592     if (fb->format->depth == 16)
0593         regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
0594     if (drm->client.device.info.chipset >= 0x11)
0595         regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
0596 
0597     regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
0598     regp->tv_setup = 0;
0599 
0600     nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
0601 
0602     /* Some values the blob sets */
0603     regp->ramdac_8c0 = 0x100;
0604     regp->ramdac_a20 = 0x0;
0605     regp->ramdac_a24 = 0xfffff;
0606     regp->ramdac_a34 = 0x1;
0607 }
0608 
0609 static int
0610 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
0611 {
0612     struct nv04_display *disp = nv04_display(crtc->dev);
0613     struct drm_framebuffer *fb = crtc->primary->fb;
0614     struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]);
0615     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0616     int ret;
0617 
0618     ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false);
0619     if (ret == 0) {
0620         if (disp->image[nv_crtc->index])
0621             nouveau_bo_unpin(disp->image[nv_crtc->index]);
0622         nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]);
0623     }
0624 
0625     return ret;
0626 }
0627 
0628 /**
0629  * Sets up registers for the given mode/adjusted_mode pair.
0630  *
0631  * The clocks, CRTCs and outputs attached to this CRTC must be off.
0632  *
0633  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
0634  * be easily turned on/off after this.
0635  */
0636 static int
0637 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
0638          struct drm_display_mode *adjusted_mode,
0639          int x, int y, struct drm_framebuffer *old_fb)
0640 {
0641     struct drm_device *dev = crtc->dev;
0642     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0643     struct nouveau_drm *drm = nouveau_drm(dev);
0644     int ret;
0645 
0646     NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
0647     drm_mode_debug_printmodeline(adjusted_mode);
0648 
0649     ret = nv_crtc_swap_fbs(crtc, old_fb);
0650     if (ret)
0651         return ret;
0652 
0653     /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
0654     nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
0655 
0656     nv_crtc_mode_set_vga(crtc, adjusted_mode);
0657     /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
0658     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
0659         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
0660     nv_crtc_mode_set_regs(crtc, adjusted_mode);
0661     nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
0662     return 0;
0663 }
0664 
0665 static void nv_crtc_save(struct drm_crtc *crtc)
0666 {
0667     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0668     struct drm_device *dev = crtc->dev;
0669     struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
0670     struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
0671     struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
0672     struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
0673 
0674     if (nv_two_heads(crtc->dev))
0675         NVSetOwner(crtc->dev, nv_crtc->index);
0676 
0677     nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
0678 
0679     /* init some state to saved value */
0680     state->sel_clk = saved->sel_clk & ~(0x5 << 16);
0681     crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
0682     state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
0683     crtc_state->gpio_ext = crtc_saved->gpio_ext;
0684 }
0685 
0686 static void nv_crtc_restore(struct drm_crtc *crtc)
0687 {
0688     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0689     struct drm_device *dev = crtc->dev;
0690     int head = nv_crtc->index;
0691     uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
0692 
0693     if (nv_two_heads(crtc->dev))
0694         NVSetOwner(crtc->dev, head);
0695 
0696     nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
0697     nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
0698 
0699     nv_crtc->last_dpms = NV_DPMS_CLEARED;
0700 }
0701 
0702 static void nv_crtc_prepare(struct drm_crtc *crtc)
0703 {
0704     struct drm_device *dev = crtc->dev;
0705     struct nouveau_drm *drm = nouveau_drm(dev);
0706     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0707     const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
0708 
0709     if (nv_two_heads(dev))
0710         NVSetOwner(dev, nv_crtc->index);
0711 
0712     drm_crtc_vblank_off(crtc);
0713     funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
0714 
0715     NVBlankScreen(dev, nv_crtc->index, true);
0716 
0717     /* Some more preparation. */
0718     NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
0719     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
0720         uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
0721         NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
0722     }
0723 }
0724 
0725 static void nv_crtc_commit(struct drm_crtc *crtc)
0726 {
0727     struct drm_device *dev = crtc->dev;
0728     const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
0729     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0730 
0731     nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
0732     nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
0733 
0734 #ifdef __BIG_ENDIAN
0735     /* turn on LFB swapping */
0736     {
0737         uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
0738         tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
0739         NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
0740     }
0741 #endif
0742 
0743     funcs->dpms(crtc, DRM_MODE_DPMS_ON);
0744     drm_crtc_vblank_on(crtc);
0745 }
0746 
0747 static void nv_crtc_destroy(struct drm_crtc *crtc)
0748 {
0749     struct nv04_display *disp = nv04_display(crtc->dev);
0750     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0751 
0752     if (!nv_crtc)
0753         return;
0754 
0755     drm_crtc_cleanup(crtc);
0756 
0757     if (disp->image[nv_crtc->index])
0758         nouveau_bo_unpin(disp->image[nv_crtc->index]);
0759     nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
0760 
0761     nouveau_bo_unmap(nv_crtc->cursor.nvbo);
0762     nouveau_bo_unpin(nv_crtc->cursor.nvbo);
0763     nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
0764     nvif_notify_dtor(&nv_crtc->vblank);
0765     kfree(nv_crtc);
0766 }
0767 
0768 static void
0769 nv_crtc_gamma_load(struct drm_crtc *crtc)
0770 {
0771     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0772     struct drm_device *dev = nv_crtc->base.dev;
0773     struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
0774     u16 *r, *g, *b;
0775     int i;
0776 
0777     rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
0778     r = crtc->gamma_store;
0779     g = r + crtc->gamma_size;
0780     b = g + crtc->gamma_size;
0781 
0782     for (i = 0; i < 256; i++) {
0783         rgbs[i].r = *r++ >> 8;
0784         rgbs[i].g = *g++ >> 8;
0785         rgbs[i].b = *b++ >> 8;
0786     }
0787 
0788     nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
0789 }
0790 
0791 static void
0792 nv_crtc_disable(struct drm_crtc *crtc)
0793 {
0794     struct nv04_display *disp = nv04_display(crtc->dev);
0795     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0796     if (disp->image[nv_crtc->index])
0797         nouveau_bo_unpin(disp->image[nv_crtc->index]);
0798     nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
0799 }
0800 
0801 static int
0802 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
0803           uint32_t size,
0804           struct drm_modeset_acquire_ctx *ctx)
0805 {
0806     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0807 
0808     /* We need to know the depth before we upload, but it's possible to
0809      * get called before a framebuffer is bound.  If this is the case,
0810      * mark the lut values as dirty by setting depth==0, and it'll be
0811      * uploaded on the first mode_set_base()
0812      */
0813     if (!nv_crtc->base.primary->fb) {
0814         nv_crtc->lut.depth = 0;
0815         return 0;
0816     }
0817 
0818     nv_crtc_gamma_load(crtc);
0819 
0820     return 0;
0821 }
0822 
0823 static int
0824 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
0825                struct drm_framebuffer *passed_fb,
0826                int x, int y, bool atomic)
0827 {
0828     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0829     struct drm_device *dev = crtc->dev;
0830     struct nouveau_drm *drm = nouveau_drm(dev);
0831     struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0832     struct nouveau_bo *nvbo;
0833     struct drm_framebuffer *drm_fb;
0834     int arb_burst, arb_lwm;
0835 
0836     NV_DEBUG(drm, "index %d\n", nv_crtc->index);
0837 
0838     /* no fb bound */
0839     if (!atomic && !crtc->primary->fb) {
0840         NV_DEBUG(drm, "No FB bound\n");
0841         return 0;
0842     }
0843 
0844     /* If atomic, we want to switch to the fb we were passed, so
0845      * now we update pointers to do that.
0846      */
0847     if (atomic) {
0848         drm_fb = passed_fb;
0849     } else {
0850         drm_fb = crtc->primary->fb;
0851     }
0852 
0853     nvbo = nouveau_gem_object(drm_fb->obj[0]);
0854     nv_crtc->fb.offset = nvbo->offset;
0855 
0856     if (nv_crtc->lut.depth != drm_fb->format->depth) {
0857         nv_crtc->lut.depth = drm_fb->format->depth;
0858         nv_crtc_gamma_load(crtc);
0859     }
0860 
0861     /* Update the framebuffer format. */
0862     regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
0863     regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;
0864     regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
0865     if (drm_fb->format->depth == 16)
0866         regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
0867     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
0868     NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
0869               regp->ramdac_gen_ctrl);
0870 
0871     regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
0872     regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
0873         XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
0874     regp->CRTC[NV_CIO_CRE_42] =
0875         XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
0876     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
0877     crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
0878     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
0879 
0880     /* Update the framebuffer location. */
0881     regp->fb_start = nv_crtc->fb.offset & ~3;
0882     regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
0883     nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
0884 
0885     /* Update the arbitration parameters. */
0886     nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
0887              &arb_burst, &arb_lwm);
0888 
0889     regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
0890     regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
0891     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
0892     crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
0893 
0894     if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
0895         regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
0896         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
0897     }
0898 
0899     return 0;
0900 }
0901 
0902 static int
0903 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
0904             struct drm_framebuffer *old_fb)
0905 {
0906     int ret = nv_crtc_swap_fbs(crtc, old_fb);
0907     if (ret)
0908         return ret;
0909     return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
0910 }
0911 
0912 static int
0913 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
0914                    struct drm_framebuffer *fb,
0915                    int x, int y, enum mode_set_atomic state)
0916 {
0917     struct nouveau_drm *drm = nouveau_drm(crtc->dev);
0918     struct drm_device *dev = drm->dev;
0919 
0920     if (state == ENTER_ATOMIC_MODE_SET)
0921         nouveau_fbcon_accel_save_disable(dev);
0922     else
0923         nouveau_fbcon_accel_restore(dev);
0924 
0925     return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
0926 }
0927 
0928 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
0929                    struct nouveau_bo *dst)
0930 {
0931     int width = nv_cursor_width(dev);
0932     uint32_t pixel;
0933     int i, j;
0934 
0935     for (i = 0; i < width; i++) {
0936         for (j = 0; j < width; j++) {
0937             pixel = nouveau_bo_rd32(src, i*64 + j);
0938 
0939             nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
0940                      | (pixel & 0xf80000) >> 9
0941                      | (pixel & 0xf800) >> 6
0942                      | (pixel & 0xf8) >> 3);
0943         }
0944     }
0945 }
0946 
0947 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
0948                    struct nouveau_bo *dst)
0949 {
0950     uint32_t pixel;
0951     int alpha, i;
0952 
0953     /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
0954      * cursors (though NPM in combination with fp dithering may not work on
0955      * nv11, from "nv" driver history)
0956      * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
0957      * blob uses, however we get given PM cursors so we use PM mode
0958      */
0959     for (i = 0; i < 64 * 64; i++) {
0960         pixel = nouveau_bo_rd32(src, i);
0961 
0962         /* hw gets unhappy if alpha <= rgb values.  for a PM image "less
0963          * than" shouldn't happen; fix "equal to" case by adding one to
0964          * alpha channel (slightly inaccurate, but so is attempting to
0965          * get back to NPM images, due to limits of integer precision)
0966          */
0967         alpha = pixel >> 24;
0968         if (alpha > 0 && alpha < 255)
0969             pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
0970 
0971 #ifdef __BIG_ENDIAN
0972         {
0973             struct nouveau_drm *drm = nouveau_drm(dev);
0974 
0975             if (drm->client.device.info.chipset == 0x11) {
0976                 pixel = ((pixel & 0x000000ff) << 24) |
0977                     ((pixel & 0x0000ff00) << 8) |
0978                     ((pixel & 0x00ff0000) >> 8) |
0979                     ((pixel & 0xff000000) >> 24);
0980             }
0981         }
0982 #endif
0983 
0984         nouveau_bo_wr32(dst, i, pixel);
0985     }
0986 }
0987 
0988 static int
0989 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
0990              uint32_t buffer_handle, uint32_t width, uint32_t height)
0991 {
0992     struct nouveau_drm *drm = nouveau_drm(crtc->dev);
0993     struct drm_device *dev = drm->dev;
0994     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
0995     struct nouveau_bo *cursor = NULL;
0996     struct drm_gem_object *gem;
0997     int ret = 0;
0998 
0999     if (!buffer_handle) {
1000         nv_crtc->cursor.hide(nv_crtc, true);
1001         return 0;
1002     }
1003 
1004     if (width != 64 || height != 64)
1005         return -EINVAL;
1006 
1007     gem = drm_gem_object_lookup(file_priv, buffer_handle);
1008     if (!gem)
1009         return -ENOENT;
1010     cursor = nouveau_gem_object(gem);
1011 
1012     ret = nouveau_bo_map(cursor);
1013     if (ret)
1014         goto out;
1015 
1016     if (drm->client.device.info.chipset >= 0x11)
1017         nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1018     else
1019         nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1020 
1021     nouveau_bo_unmap(cursor);
1022     nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset;
1023     nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1024     nv_crtc->cursor.show(nv_crtc, true);
1025 out:
1026     drm_gem_object_put(gem);
1027     return ret;
1028 }
1029 
1030 static int
1031 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1032 {
1033     struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1034 
1035     nv_crtc->cursor.set_pos(nv_crtc, x, y);
1036     return 0;
1037 }
1038 
1039 struct nv04_page_flip_state {
1040     struct list_head head;
1041     struct drm_pending_vblank_event *event;
1042     struct drm_crtc *crtc;
1043     int bpp, pitch;
1044     u64 offset;
1045 };
1046 
1047 static int
1048 nv04_finish_page_flip(struct nouveau_channel *chan,
1049               struct nv04_page_flip_state *ps)
1050 {
1051     struct nouveau_fence_chan *fctx = chan->fence;
1052     struct nouveau_drm *drm = chan->drm;
1053     struct drm_device *dev = drm->dev;
1054     struct nv04_page_flip_state *s;
1055     unsigned long flags;
1056 
1057     spin_lock_irqsave(&dev->event_lock, flags);
1058 
1059     if (list_empty(&fctx->flip)) {
1060         NV_ERROR(drm, "unexpected pageflip\n");
1061         spin_unlock_irqrestore(&dev->event_lock, flags);
1062         return -EINVAL;
1063     }
1064 
1065     s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head);
1066     if (s->event) {
1067         drm_crtc_arm_vblank_event(s->crtc, s->event);
1068     } else {
1069         /* Give up ownership of vblank for page-flipped crtc */
1070         drm_crtc_vblank_put(s->crtc);
1071     }
1072 
1073     list_del(&s->head);
1074     if (ps)
1075         *ps = *s;
1076     kfree(s);
1077 
1078     spin_unlock_irqrestore(&dev->event_lock, flags);
1079     return 0;
1080 }
1081 
1082 int
1083 nv04_flip_complete(struct nvif_notify *notify)
1084 {
1085     struct nouveau_cli *cli = (void *)notify->object->client;
1086     struct nouveau_drm *drm = cli->drm;
1087     struct nouveau_channel *chan = drm->channel;
1088     struct nv04_page_flip_state state;
1089 
1090     if (!nv04_finish_page_flip(chan, &state)) {
1091         nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
1092                  state.offset + state.crtc->y *
1093                  state.pitch + state.crtc->x *
1094                  state.bpp / 8);
1095     }
1096 
1097     return NVIF_NOTIFY_KEEP;
1098 }
1099 
1100 static int
1101 nv04_page_flip_emit(struct nouveau_channel *chan,
1102             struct nouveau_bo *old_bo,
1103             struct nouveau_bo *new_bo,
1104             struct nv04_page_flip_state *s,
1105             struct nouveau_fence **pfence)
1106 {
1107     struct nouveau_fence_chan *fctx = chan->fence;
1108     struct nouveau_drm *drm = chan->drm;
1109     struct drm_device *dev = drm->dev;
1110     struct nvif_push *push = chan->chan.push;
1111     unsigned long flags;
1112     int ret;
1113 
1114     /* Queue it to the pending list */
1115     spin_lock_irqsave(&dev->event_lock, flags);
1116     list_add_tail(&s->head, &fctx->flip);
1117     spin_unlock_irqrestore(&dev->event_lock, flags);
1118 
1119     /* Synchronize with the old framebuffer */
1120     ret = nouveau_fence_sync(old_bo, chan, false, false);
1121     if (ret)
1122         goto fail;
1123 
1124     /* Emit the pageflip */
1125     ret = PUSH_WAIT(push, 2);
1126     if (ret)
1127         goto fail;
1128 
1129     PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
1130     PUSH_KICK(push);
1131 
1132     ret = nouveau_fence_new(chan, false, pfence);
1133     if (ret)
1134         goto fail;
1135 
1136     return 0;
1137 fail:
1138     spin_lock_irqsave(&dev->event_lock, flags);
1139     list_del(&s->head);
1140     spin_unlock_irqrestore(&dev->event_lock, flags);
1141     return ret;
1142 }
1143 
1144 static int
1145 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1146             struct drm_pending_vblank_event *event, u32 flags,
1147             struct drm_modeset_acquire_ctx *ctx)
1148 {
1149     const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
1150     struct drm_device *dev = crtc->dev;
1151     struct nouveau_drm *drm = nouveau_drm(dev);
1152     struct drm_framebuffer *old_fb = crtc->primary->fb;
1153     struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]);
1154     struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]);
1155     struct nv04_page_flip_state *s;
1156     struct nouveau_channel *chan;
1157     struct nouveau_cli *cli;
1158     struct nouveau_fence *fence;
1159     struct nv04_display *dispnv04 = nv04_display(dev);
1160     struct nvif_push *push;
1161     int head = nouveau_crtc(crtc)->index;
1162     int ret;
1163 
1164     chan = drm->channel;
1165     if (!chan)
1166         return -ENODEV;
1167     cli = (void *)chan->user.client;
1168     push = chan->chan.push;
1169 
1170     s = kzalloc(sizeof(*s), GFP_KERNEL);
1171     if (!s)
1172         return -ENOMEM;
1173 
1174     if (new_bo != old_bo) {
1175         ret = nouveau_bo_pin(new_bo, NOUVEAU_GEM_DOMAIN_VRAM, true);
1176         if (ret)
1177             goto fail_free;
1178     }
1179 
1180     mutex_lock(&cli->mutex);
1181     ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL);
1182     if (ret)
1183         goto fail_unpin;
1184 
1185     /* synchronise rendering channel with the kernel's channel */
1186     ret = nouveau_fence_sync(new_bo, chan, false, true);
1187     if (ret) {
1188         ttm_bo_unreserve(&new_bo->bo);
1189         goto fail_unpin;
1190     }
1191 
1192     if (new_bo != old_bo) {
1193         ttm_bo_unreserve(&new_bo->bo);
1194 
1195         ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL);
1196         if (ret)
1197             goto fail_unpin;
1198     }
1199 
1200     /* Initialize a page flip struct */
1201     *s = (struct nv04_page_flip_state)
1202         { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
1203           new_bo->offset };
1204 
1205     /* Keep vblanks on during flip, for the target crtc of this flip */
1206     drm_crtc_vblank_get(crtc);
1207 
1208     /* Emit a page flip */
1209     if (swap_interval) {
1210         ret = PUSH_WAIT(push, 8);
1211         if (ret)
1212             goto fail_unreserve;
1213 
1214         PUSH_NVSQ(push, NV05F, 0x012c, 0);
1215         PUSH_NVSQ(push, NV05F, 0x0134, head);
1216         PUSH_NVSQ(push, NV05F, 0x0100, 0);
1217         PUSH_NVSQ(push, NV05F, 0x0130, 0);
1218     }
1219 
1220     nouveau_bo_ref(new_bo, &dispnv04->image[head]);
1221 
1222     ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence);
1223     if (ret)
1224         goto fail_unreserve;
1225     mutex_unlock(&cli->mutex);
1226 
1227     /* Update the crtc struct and cleanup */
1228     crtc->primary->fb = fb;
1229 
1230     nouveau_bo_fence(old_bo, fence, false);
1231     ttm_bo_unreserve(&old_bo->bo);
1232     if (old_bo != new_bo)
1233         nouveau_bo_unpin(old_bo);
1234     nouveau_fence_unref(&fence);
1235     return 0;
1236 
1237 fail_unreserve:
1238     drm_crtc_vblank_put(crtc);
1239     ttm_bo_unreserve(&old_bo->bo);
1240 fail_unpin:
1241     mutex_unlock(&cli->mutex);
1242     if (old_bo != new_bo)
1243         nouveau_bo_unpin(new_bo);
1244 fail_free:
1245     kfree(s);
1246     return ret;
1247 }
1248 
1249 static const struct drm_crtc_funcs nv04_crtc_funcs = {
1250     .cursor_set = nv04_crtc_cursor_set,
1251     .cursor_move = nv04_crtc_cursor_move,
1252     .gamma_set = nv_crtc_gamma_set,
1253     .set_config = drm_crtc_helper_set_config,
1254     .page_flip = nv04_crtc_page_flip,
1255     .destroy = nv_crtc_destroy,
1256     .enable_vblank = nouveau_display_vblank_enable,
1257     .disable_vblank = nouveau_display_vblank_disable,
1258     .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1259 };
1260 
1261 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1262     .dpms = nv_crtc_dpms,
1263     .prepare = nv_crtc_prepare,
1264     .commit = nv_crtc_commit,
1265     .mode_set = nv_crtc_mode_set,
1266     .mode_set_base = nv04_crtc_mode_set_base,
1267     .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1268     .disable = nv_crtc_disable,
1269     .get_scanout_position = nouveau_display_scanoutpos,
1270 };
1271 
1272 static const uint32_t modeset_formats[] = {
1273         DRM_FORMAT_XRGB8888,
1274         DRM_FORMAT_RGB565,
1275         DRM_FORMAT_XRGB1555,
1276 };
1277 
1278 static struct drm_plane *
1279 create_primary_plane(struct drm_device *dev)
1280 {
1281         struct drm_plane *primary;
1282         int ret;
1283 
1284         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1285         if (primary == NULL) {
1286                 DRM_DEBUG_KMS("Failed to allocate primary plane\n");
1287                 return NULL;
1288         }
1289 
1290         /* possible_crtc's will be filled in later by crtc_init */
1291         ret = drm_universal_plane_init(dev, primary, 0,
1292                                        &drm_primary_helper_funcs,
1293                                        modeset_formats,
1294                                        ARRAY_SIZE(modeset_formats), NULL,
1295                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1296         if (ret) {
1297                 kfree(primary);
1298                 primary = NULL;
1299         }
1300 
1301         return primary;
1302 }
1303 
1304 static int nv04_crtc_vblank_handler(struct nvif_notify *notify)
1305 {
1306     struct nouveau_crtc *nv_crtc =
1307         container_of(notify, struct nouveau_crtc, vblank);
1308 
1309     drm_crtc_handle_vblank(&nv_crtc->base);
1310     return NVIF_NOTIFY_KEEP;
1311 }
1312 
1313 int
1314 nv04_crtc_create(struct drm_device *dev, int crtc_num)
1315 {
1316     struct nouveau_display *disp = nouveau_display(dev);
1317     struct nouveau_crtc *nv_crtc;
1318     int ret;
1319 
1320     nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1321     if (!nv_crtc)
1322         return -ENOMEM;
1323 
1324     nv_crtc->lut.depth = 0;
1325 
1326     nv_crtc->index = crtc_num;
1327     nv_crtc->last_dpms = NV_DPMS_CLEARED;
1328 
1329     nv_crtc->save = nv_crtc_save;
1330     nv_crtc->restore = nv_crtc_restore;
1331 
1332     drm_crtc_init_with_planes(dev, &nv_crtc->base,
1333                                   create_primary_plane(dev), NULL,
1334                                   &nv04_crtc_funcs, NULL);
1335     drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1336     drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1337 
1338     ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100,
1339                  NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL,
1340                  &nv_crtc->cursor.nvbo);
1341     if (!ret) {
1342         ret = nouveau_bo_pin(nv_crtc->cursor.nvbo,
1343                      NOUVEAU_GEM_DOMAIN_VRAM, false);
1344         if (!ret) {
1345             ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1346             if (ret)
1347                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1348         }
1349         if (ret)
1350             nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1351     }
1352 
1353     nv04_cursor_init(nv_crtc);
1354 
1355     ret = nvif_notify_ctor(&disp->disp.object, "kmsVbl", nv04_crtc_vblank_handler,
1356                    false, NV04_DISP_NTFY_VBLANK,
1357                    &(struct nvif_notify_head_req_v0) {
1358                     .head = nv_crtc->index,
1359                    },
1360                    sizeof(struct nvif_notify_head_req_v0),
1361                    sizeof(struct nvif_notify_head_rep_v0),
1362                    &nv_crtc->vblank);
1363 
1364     return ret;
1365 }
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