nouveau/dispnv04/arb.c

0001 /*
0002  * Copyright 1993-2003 NVIDIA, Corporation
0003  * Copyright 2007-2009 Stuart Bennett
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0019  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
0020  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0021  * SOFTWARE.
0022  */
0023
0024 #include "nouveau_drv.h"
0025 #include "nouveau_reg.h"
0026 #include "hw.h"
0027
0028 /****************************************************************************\
0029 *                                                                            *
0030 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
0031 * the snow seen when accessing the framebuffer without it.                   *
0032 * It just works (I hope).                                                    *
0033 *                                                                            *
0034 \****************************************************************************/
0035
0036 struct nv_fifo_info {
0037     int lwm;
0038     int burst;
0039 };
0040
0041 struct nv_sim_state {
0042     int pclk_khz;
0043     int mclk_khz;
0044     int nvclk_khz;
0045     int bpp;
0046     int mem_page_miss;
0047     int mem_latency;
0048     int memory_type;
0049     int memory_width;
0050     int two_heads;
0051 };
0052
0053 static void
0054 nv04_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
0055 {
0056     int pagemiss, cas, bpp;
0057     int nvclks, mclks, crtpagemiss;
0058     int found, mclk_extra, mclk_loop, cbs, m1, p1;
0059     int mclk_freq, pclk_freq, nvclk_freq;
0060     int us_m, us_n, us_p, crtc_drain_rate;
0061     int cpm_us, us_crt, clwm;
0062
0063     pclk_freq = arb->pclk_khz;
0064     mclk_freq = arb->mclk_khz;
0065     nvclk_freq = arb->nvclk_khz;
0066     pagemiss = arb->mem_page_miss;
0067     cas = arb->mem_latency;
0068     bpp = arb->bpp;
0069     cbs = 128;
0070
0071     nvclks = 10;
0072     mclks = 13 + cas;
0073     mclk_extra = 3;
0074     found = 0;
0075
0076     while (!found) {
0077         found = 1;
0078
0079         mclk_loop = mclks + mclk_extra;
0080         us_m = mclk_loop * 1000 * 1000 / mclk_freq;
0081         us_n = nvclks * 1000 * 1000 / nvclk_freq;
0082         us_p = nvclks * 1000 * 1000 / pclk_freq;
0083
0084         crtc_drain_rate = pclk_freq * bpp / 8;
0085         crtpagemiss = 2;
0086         crtpagemiss += 1;
0087         cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
0088         us_crt = cpm_us + us_m + us_n + us_p;
0089         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
0090         clwm++;
0091
0092         m1 = clwm + cbs - 512;
0093         p1 = m1 * pclk_freq / mclk_freq;
0094         p1 = p1 * bpp / 8;
0095         if ((p1 < m1 && m1 > 0) || clwm > 519) {
0096             found = !mclk_extra;
0097             mclk_extra--;
0098         }
0099         if (clwm < 384)
0100             clwm = 384;
0101
0102         fifo->lwm = clwm;
0103         fifo->burst = cbs;
0104     }
0105 }
0106
0107 static void
0108 nv10_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
0109 {
0110     int fill_rate, drain_rate;
0111     int pclks, nvclks, mclks, xclks;
0112     int pclk_freq, nvclk_freq, mclk_freq;
0113     int fill_lat, extra_lat;
0114     int max_burst_o, max_burst_l;
0115     int fifo_len, min_lwm, max_lwm;
0116     const int burst_lat = 80; /* Maximum allowable latency due
0117                    * to the CRTC FIFO burst. (ns) */
0118
0119     pclk_freq = arb->pclk_khz;
0120     nvclk_freq = arb->nvclk_khz;
0121     mclk_freq = arb->mclk_khz;
0122
0123     fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */
0124     drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */
0125
0126     fifo_len = arb->two_heads ? 1536 : 1024; /* B */
0127
0128     /* Fixed FIFO refill latency. */
0129
0130     pclks = 4;  /* lwm detect. */
0131
0132     nvclks = 3  /* lwm -> sync. */
0133         + 2 /* fbi bus cycles (1 req + 1 busy) */
0134         + 1 /* 2 edge sync.  may be very close to edge so
0135              * just put one. */
0136         + 1 /* fbi_d_rdv_n */
0137         + 1 /* Fbi_d_rdata */
0138         + 1;    /* crtfifo load */
0139
0140     mclks = 1   /* 2 edge sync.  may be very close to edge so
0141              * just put one. */
0142         + 1 /* arb_hp_req */
0143         + 5 /* tiling pipeline */
0144         + 2 /* latency fifo */
0145         + 2 /* memory request to fbio block */
0146         + 7;    /* data returned from fbio block */
0147
0148     /* Need to accumulate 256 bits for read */
0149     mclks += (arb->memory_type == 0 ? 2 : 1)
0150         * arb->memory_width / 32;
0151
0152     fill_lat = mclks * 1000 * 1000 / mclk_freq   /* minimum mclk latency */
0153         + nvclks * 1000 * 1000 / nvclk_freq  /* nvclk latency */
0154         + pclks * 1000 * 1000 / pclk_freq;   /* pclk latency */
0155
0156     /* Conditional FIFO refill latency. */
0157
0158     xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to
0159                         * the overlay. */
0160         + 2 * arb->mem_page_miss       /* Extra pagemiss latency. */
0161         + (arb->bpp == 32 ? 8 : 4);    /* Margin of error. */
0162
0163     extra_lat = xclks * 1000 * 1000 / mclk_freq;
0164
0165     if (arb->two_heads)
0166         /* Account for another CRTC. */
0167         extra_lat += fill_lat + extra_lat + burst_lat;
0168
0169     /* FIFO burst */
0170
0171     /* Max burst not leading to overflows. */
0172     max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000))
0173         * (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000);
0174     fifo->burst = min(max_burst_o, 1024);
0175
0176     /* Max burst value with an acceptable latency. */
0177     max_burst_l = burst_lat * fill_rate / (1000 * 1000);
0178     fifo->burst = min(max_burst_l, fifo->burst);
0179
0180     fifo->burst = rounddown_pow_of_two(fifo->burst);
0181
0182     /* FIFO low watermark */
0183
0184     min_lwm = (fill_lat + extra_lat) * drain_rate / (1000 * 1000) + 1;
0185     max_lwm = fifo_len - fifo->burst
0186         + fill_lat * drain_rate / (1000 * 1000)
0187         + fifo->burst * drain_rate / fill_rate;
0188
0189     fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */
0190 }
0191
0192 static void
0193 nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
0194         int *burst, int *lwm)
0195 {
0196     struct nouveau_drm *drm = nouveau_drm(dev);
0197     struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
0198     struct nv_fifo_info fifo_data;
0199     struct nv_sim_state sim_data;
0200     int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
0201     int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
0202     uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
0203     struct pci_dev *pdev = to_pci_dev(dev->dev);
0204
0205     sim_data.pclk_khz = VClk;
0206     sim_data.mclk_khz = MClk;
0207     sim_data.nvclk_khz = NVClk;
0208     sim_data.bpp = bpp;
0209     sim_data.two_heads = nv_two_heads(dev);
0210     if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
0211         (pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
0212         uint32_t type;
0213         int domain = pci_domain_nr(pdev->bus);
0214
0215         pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
0216                       0x7c, &type);
0217
0218         sim_data.memory_type = (type >> 12) & 1;
0219         sim_data.memory_width = 64;
0220         sim_data.mem_latency = 3;
0221         sim_data.mem_page_miss = 10;
0222     } else {
0223         sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;
0224         sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
0225         sim_data.mem_latency = cfg1 & 0xf;
0226         sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
0227     }
0228
0229     if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT)
0230         nv04_calc_arb(&fifo_data, &sim_data);
0231     else
0232         nv10_calc_arb(&fifo_data, &sim_data);
0233
0234     *burst = ilog2(fifo_data.burst >> 4);
0235     *lwm = fifo_data.lwm >> 3;
0236 }
0237
0238 static void
0239 nv20_update_arb(int *burst, int *lwm)
0240 {
0241     unsigned int fifo_size, burst_size, graphics_lwm;
0242
0243     fifo_size = 2048;
0244     burst_size = 512;
0245     graphics_lwm = fifo_size - burst_size;
0246
0247     *burst = ilog2(burst_size >> 5);
0248     *lwm = graphics_lwm >> 3;
0249 }
0250
0251 void
0252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
0253 {
0254     struct nouveau_drm *drm = nouveau_drm(dev);
0255     struct pci_dev *pdev = to_pci_dev(dev->dev);
0256
0257     if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
0258         nv04_update_arb(dev, vclk, bpp, burst, lwm);
0259     else if ((pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
0260          (pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
0261         *burst = 128;
0262         *lwm = 0x0480;
0263     } else
0264         nv20_update_arb(burst, lwm);
0265 }