drm/msm/msm_fence.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2013-2016 Red Hat
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006
0007 #ifndef __MSM_FENCE_H__
0008 #define __MSM_FENCE_H__
0009
0010 #include "msm_drv.h"
0011
0012 /**
0013  * struct msm_fence_context - fence context for gpu
0014  *
0015  * Each ringbuffer has a single fence context, with the GPU writing an
0016  * incrementing fence seqno at the end of each submit
0017  */
0018 struct msm_fence_context {
0019     struct drm_device *dev;
0020     /** name: human readable name for fence timeline */
0021     char name[32];
0022     /** context: see dma_fence_context_alloc() */
0023     unsigned context;
0024     /** index: similar to context, but local to msm_fence_context's */
0025     unsigned index;
0026
0027     /**
0028      * last_fence:
0029      *
0030      * Last assigned fence, incremented each time a fence is created
0031      * on this fence context.  If last_fence == completed_fence,
0032      * there is no remaining pending work
0033      */
0034     uint32_t last_fence;
0035
0036     /**
0037      * completed_fence:
0038      *
0039      * The last completed fence, updated from the CPU after interrupt
0040      * from GPU
0041      */
0042     uint32_t completed_fence;
0043
0044     /**
0045      * fenceptr:
0046      *
0047      * The address that the GPU directly writes with completed fence
0048      * seqno.  This can be ahead of completed_fence.  We can peek at
0049      * this to see if a fence has already signaled but the CPU hasn't
0050      * gotten around to handling the irq and updating completed_fence
0051      */
0052     volatile uint32_t *fenceptr;
0053
0054     spinlock_t spinlock;
0055 };
0056
0057 struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev,
0058         volatile uint32_t *fenceptr, const char *name);
0059 void msm_fence_context_free(struct msm_fence_context *fctx);
0060
0061 bool msm_fence_completed(struct msm_fence_context *fctx, uint32_t fence);
0062 void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence);
0063
0064 struct dma_fence * msm_fence_alloc(struct msm_fence_context *fctx);
0065
0066 static inline bool
0067 fence_before(uint32_t a, uint32_t b)
0068 {
0069    return (int32_t)(a - b) < 0;
0070 }
0071
0072 static inline bool
0073 fence_after(uint32_t a, uint32_t b)
0074 {
0075    return (int32_t)(a - b) > 0;
0076 }
0077
0078 #endif