drm/msm/msm_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
0004  * Copyright (C) 2013 Red Hat
0005  * Author: Rob Clark <robdclark@gmail.com>
0006  */
0007
0008 #ifndef __MSM_DRV_H__
0009 #define __MSM_DRV_H__
0010
0011 #include <linux/kernel.h>
0012 #include <linux/clk.h>
0013 #include <linux/cpufreq.h>
0014 #include <linux/module.h>
0015 #include <linux/component.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/slab.h>
0020 #include <linux/list.h>
0021 #include <linux/iommu.h>
0022 #include <linux/types.h>
0023 #include <linux/of_graph.h>
0024 #include <linux/of_device.h>
0025 #include <linux/sizes.h>
0026 #include <linux/kthread.h>
0027
0028 #include <drm/drm_atomic.h>
0029 #include <drm/drm_atomic_helper.h>
0030 #include <drm/drm_plane_helper.h>
0031 #include <drm/drm_probe_helper.h>
0032 #include <drm/drm_fb_helper.h>
0033 #include <drm/display/drm_dsc.h>
0034 #include <drm/msm_drm.h>
0035 #include <drm/drm_gem.h>
0036
0037 struct msm_kms;
0038 struct msm_gpu;
0039 struct msm_mmu;
0040 struct msm_mdss;
0041 struct msm_rd_state;
0042 struct msm_perf_state;
0043 struct msm_gem_submit;
0044 struct msm_fence_context;
0045 struct msm_gem_address_space;
0046 struct msm_gem_vma;
0047 struct msm_disp_state;
0048
0049 #define MAX_CRTCS      8
0050 #define MAX_BRIDGES    8
0051
0052 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
0053
0054 enum msm_dp_controller {
0055     MSM_DP_CONTROLLER_0,
0056     MSM_DP_CONTROLLER_1,
0057     MSM_DP_CONTROLLER_2,
0058     MSM_DP_CONTROLLER_COUNT,
0059 };
0060
0061 #define MSM_GPU_MAX_RINGS 4
0062 #define MAX_H_TILES_PER_DISPLAY 2
0063
0064 /**
0065  * enum msm_event_wait - type of HW events to wait for
0066  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
0067  * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
0068  * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
0069  */
0070 enum msm_event_wait {
0071     MSM_ENC_COMMIT_DONE = 0,
0072     MSM_ENC_TX_COMPLETE,
0073     MSM_ENC_VBLANK,
0074 };
0075
0076 /**
0077  * struct msm_display_topology - defines a display topology pipeline
0078  * @num_lm:       number of layer mixers used
0079  * @num_enc:      number of compression encoder blocks used
0080  * @num_intf:     number of interfaces the panel is mounted on
0081  * @num_dspp:     number of dspp blocks used
0082  * @num_dsc:      number of Display Stream Compression (DSC) blocks used
0083  */
0084 struct msm_display_topology {
0085     u32 num_lm;
0086     u32 num_enc;
0087     u32 num_intf;
0088     u32 num_dspp;
0089     u32 num_dsc;
0090 };
0091
0092 /* Commit/Event thread specific structure */
0093 struct msm_drm_thread {
0094     struct drm_device *dev;
0095     unsigned int crtc_id;
0096     struct kthread_worker *worker;
0097 };
0098
0099 /* DSC config */
0100 struct msm_display_dsc_config {
0101     struct drm_dsc_config *drm;
0102 };
0103
0104 struct msm_drm_private {
0105
0106     struct drm_device *dev;
0107
0108     struct msm_kms *kms;
0109     int (*kms_init)(struct drm_device *dev);
0110
0111     /* subordinate devices, if present: */
0112     struct platform_device *gpu_pdev;
0113
0114     /* possibly this should be in the kms component, but it is
0115      * shared by both mdp4 and mdp5..
0116      */
0117     struct hdmi *hdmi;
0118
0119     /* DSI is shared by mdp4 and mdp5 */
0120     struct msm_dsi *dsi[2];
0121
0122     struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
0123
0124     /* when we have more than one 'msm_gpu' these need to be an array: */
0125     struct msm_gpu *gpu;
0126
0127     /* gpu is only set on open(), but we need this info earlier */
0128     bool is_a2xx;
0129     bool has_cached_coherent;
0130
0131     struct drm_fb_helper *fbdev;
0132
0133     struct msm_rd_state *rd;       /* debugfs to dump all submits */
0134     struct msm_rd_state *hangrd;   /* debugfs to dump hanging submits */
0135     struct msm_perf_state *perf;
0136
0137     /**
0138      * List of all GEM objects (mainly for debugfs, protected by obj_lock
0139      * (acquire before per GEM object lock)
0140      */
0141     struct list_head objects;
0142     struct mutex obj_lock;
0143
0144     /**
0145      * LRUs of inactive GEM objects.  Every bo is either in one of the
0146      * inactive lists (depending on whether or not it is shrinkable) or
0147      * gpu->active_list (for the gpu it is active on[1]), or transiently
0148      * on a temporary list as the shrinker is running.
0149      *
0150      * Note that inactive_willneed also contains pinned and vmap'd bos,
0151      * but the number of pinned-but-not-active objects is small (scanout
0152      * buffers, ringbuffer, etc).
0153      *
0154      * These lists are protected by mm_lock (which should be acquired
0155      * before per GEM object lock).  One should *not* hold mm_lock in
0156      * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
0157      *
0158      * [1] if someone ever added support for the old 2d cores, there could be
0159      *     more than one gpu object
0160      */
0161     struct list_head inactive_willneed;  /* inactive + potentially unpin/evictable */
0162     struct list_head inactive_dontneed;  /* inactive + shrinkable */
0163     struct list_head inactive_unpinned;  /* inactive + purged or unpinned */
0164     long shrinkable_count;               /* write access under mm_lock */
0165     long evictable_count;                /* write access under mm_lock */
0166     struct mutex mm_lock;
0167
0168     struct workqueue_struct *wq;
0169
0170     unsigned int num_crtcs;
0171     struct drm_crtc *crtcs[MAX_CRTCS];
0172
0173     struct msm_drm_thread event_thread[MAX_CRTCS];
0174
0175     unsigned int num_bridges;
0176     struct drm_bridge *bridges[MAX_BRIDGES];
0177
0178     /* VRAM carveout, used when no IOMMU: */
0179     struct {
0180         unsigned long size;
0181         dma_addr_t paddr;
0182         /* NOTE: mm managed at the page level, size is in # of pages
0183          * and position mm_node->start is in # of pages:
0184          */
0185         struct drm_mm mm;
0186         spinlock_t lock; /* Protects drm_mm node allocation/removal */
0187     } vram;
0188
0189     struct notifier_block vmap_notifier;
0190     struct shrinker shrinker;
0191
0192     struct drm_atomic_state *pm_state;
0193
0194     /* For hang detection, in ms */
0195     unsigned int hangcheck_period;
0196
0197     /**
0198      * disable_err_irq:
0199      *
0200      * Disable handling of GPU hw error interrupts, to force fallback to
0201      * sw hangcheck timer.  Written (via debugfs) by igt tests to test
0202      * the sw hangcheck mechanism.
0203      */
0204     bool disable_err_irq;
0205 };
0206
0207 struct msm_format {
0208     uint32_t pixel_format;
0209 };
0210
0211 struct msm_pending_timer;
0212
0213 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
0214         struct msm_kms *kms, int crtc_idx);
0215 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
0216 void msm_atomic_commit_tail(struct drm_atomic_state *state);
0217 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
0218 void msm_atomic_state_clear(struct drm_atomic_state *state);
0219 void msm_atomic_state_free(struct drm_atomic_state *state);
0220
0221 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
0222 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
0223
0224 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
0225 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
0226
0227 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
0228 bool msm_use_mmu(struct drm_device *dev);
0229
0230 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
0231         struct drm_file *file);
0232
0233 #ifdef CONFIG_DEBUG_FS
0234 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
0235 #endif
0236
0237 void msm_gem_shrinker_init(struct drm_device *dev);
0238 void msm_gem_shrinker_cleanup(struct drm_device *dev);
0239
0240 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
0241 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
0242 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
0243 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
0244 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
0245         struct dma_buf_attachment *attach, struct sg_table *sg);
0246 int msm_gem_prime_pin(struct drm_gem_object *obj);
0247 void msm_gem_prime_unpin(struct drm_gem_object *obj);
0248
0249 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
0250         struct msm_gem_address_space *aspace, bool needs_dirtyfb);
0251 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
0252         struct msm_gem_address_space *aspace, bool needed_dirtyfb);
0253 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
0254         struct msm_gem_address_space *aspace, int plane);
0255 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
0256 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
0257 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
0258         struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
0259 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
0260         int w, int h, int p, uint32_t format);
0261
0262 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
0263 void msm_fbdev_free(struct drm_device *dev);
0264
0265 struct hdmi;
0266 #ifdef CONFIG_DRM_MSM_HDMI
0267 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
0268         struct drm_encoder *encoder);
0269 void __init msm_hdmi_register(void);
0270 void __exit msm_hdmi_unregister(void);
0271 #else
0272 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
0273         struct drm_encoder *encoder)
0274 {
0275     return -EINVAL;
0276 }
0277 static inline void __init msm_hdmi_register(void) {}
0278 static inline void __exit msm_hdmi_unregister(void) {}
0279 #endif
0280
0281 struct msm_dsi;
0282 #ifdef CONFIG_DRM_MSM_DSI
0283 int dsi_dev_attach(struct platform_device *pdev);
0284 void dsi_dev_detach(struct platform_device *pdev);
0285 void __init msm_dsi_register(void);
0286 void __exit msm_dsi_unregister(void);
0287 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
0288              struct drm_encoder *encoder);
0289 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
0290 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
0291 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
0292 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
0293 struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
0294 #else
0295 static inline void __init msm_dsi_register(void)
0296 {
0297 }
0298 static inline void __exit msm_dsi_unregister(void)
0299 {
0300 }
0301 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
0302                        struct drm_device *dev,
0303                        struct drm_encoder *encoder)
0304 {
0305     return -EINVAL;
0306 }
0307 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
0308 {
0309 }
0310 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
0311 {
0312     return false;
0313 }
0314 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
0315 {
0316     return false;
0317 }
0318 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
0319 {
0320     return false;
0321 }
0322
0323 static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
0324 {
0325     return NULL;
0326 }
0327 #endif
0328
0329 #ifdef CONFIG_DRM_MSM_DP
0330 int __init msm_dp_register(void);
0331 void __exit msm_dp_unregister(void);
0332 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
0333              struct drm_encoder *encoder);
0334 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
0335 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
0336
0337 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
0338 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
0339
0340 #else
0341 static inline int __init msm_dp_register(void)
0342 {
0343     return -EINVAL;
0344 }
0345 static inline void __exit msm_dp_unregister(void)
0346 {
0347 }
0348 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
0349                        struct drm_device *dev,
0350                        struct drm_encoder *encoder)
0351 {
0352     return -EINVAL;
0353 }
0354
0355 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
0356 {
0357 }
0358
0359 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
0360 {
0361 }
0362
0363 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
0364         struct drm_minor *minor)
0365 {
0366 }
0367
0368 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
0369 {
0370     return false;
0371 }
0372
0373 #endif
0374
0375 #ifdef CONFIG_DRM_MSM_MDP4
0376 void msm_mdp4_register(void);
0377 void msm_mdp4_unregister(void);
0378 #else
0379 static inline void msm_mdp4_register(void) {}
0380 static inline void msm_mdp4_unregister(void) {}
0381 #endif
0382
0383 #ifdef CONFIG_DRM_MSM_MDP5
0384 void msm_mdp_register(void);
0385 void msm_mdp_unregister(void);
0386 #else
0387 static inline void msm_mdp_register(void) {}
0388 static inline void msm_mdp_unregister(void) {}
0389 #endif
0390
0391 #ifdef CONFIG_DRM_MSM_DPU
0392 void msm_dpu_register(void);
0393 void msm_dpu_unregister(void);
0394 #else
0395 static inline void msm_dpu_register(void) {}
0396 static inline void msm_dpu_unregister(void) {}
0397 #endif
0398
0399 #ifdef CONFIG_DRM_MSM_MDSS
0400 void msm_mdss_register(void);
0401 void msm_mdss_unregister(void);
0402 #else
0403 static inline void msm_mdss_register(void) {}
0404 static inline void msm_mdss_unregister(void) {}
0405 #endif
0406
0407 #ifdef CONFIG_DEBUG_FS
0408 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
0409 int msm_debugfs_late_init(struct drm_device *dev);
0410 int msm_rd_debugfs_init(struct drm_minor *minor);
0411 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
0412 __printf(3, 4)
0413 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
0414         const char *fmt, ...);
0415 int msm_perf_debugfs_init(struct drm_minor *minor);
0416 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
0417 #else
0418 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
0419 __printf(3, 4)
0420 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
0421             struct msm_gem_submit *submit,
0422             const char *fmt, ...) {}
0423 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
0424 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
0425 #endif
0426
0427 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
0428
0429 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
0430     const char *name);
0431 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
0432 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
0433         phys_addr_t *size);
0434 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
0435
0436 #define msm_writel(data, addr) writel((data), (addr))
0437 #define msm_readl(addr) readl((addr))
0438
0439 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
0440 {
0441     u32 val = msm_readl(addr);
0442
0443     val &= ~mask;
0444     msm_writel(val | or, addr);
0445 }
0446
0447 /**
0448  * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
0449  *
0450  * @timer: hrtimer to control when the kthread work is triggered
0451  * @work:  the kthread work
0452  * @worker: the kthread worker the work will be scheduled on
0453  */
0454 struct msm_hrtimer_work {
0455     struct hrtimer timer;
0456     struct kthread_work work;
0457     struct kthread_worker *worker;
0458 };
0459
0460 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
0461                 ktime_t wakeup_time,
0462                 enum hrtimer_mode mode);
0463 void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
0464                struct kthread_worker *worker,
0465                kthread_work_func_t fn,
0466                clockid_t clock_id,
0467                enum hrtimer_mode mode);
0468
0469 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
0470 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
0471
0472 static inline int align_pitch(int width, int bpp)
0473 {
0474     int bytespp = (bpp + 7) / 8;
0475     /* adreno needs pitch aligned to 32 pixels: */
0476     return bytespp * ALIGN(width, 32);
0477 }
0478
0479 /* for the generated headers: */
0480 #define INVALID_IDX(idx) ({BUG(); 0;})
0481 #define fui(x)                ({BUG(); 0;})
0482 #define _mesa_float_to_half(x) ({BUG(); 0;})
0483
0484
0485 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
0486
0487 /* for conditionally setting boolean flag(s): */
0488 #define COND(bool, val) ((bool) ? (val) : 0)
0489
0490 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
0491 {
0492     ktime_t now = ktime_get();
0493     s64 remaining_jiffies;
0494
0495     if (ktime_compare(*timeout, now) < 0) {
0496         remaining_jiffies = 0;
0497     } else {
0498         ktime_t rem = ktime_sub(*timeout, now);
0499         remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
0500     }
0501
0502     return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
0503 }
0504
0505 /* Driver helpers */
0506
0507 extern const struct component_master_ops msm_drm_ops;
0508
0509 int msm_pm_prepare(struct device *dev);
0510 void msm_pm_complete(struct device *dev);
0511
0512 int msm_drv_probe(struct device *dev,
0513     int (*kms_init)(struct drm_device *dev));
0514 void msm_drv_shutdown(struct platform_device *pdev);
0515
0516
0517 #endif /* __MSM_DRV_H__ */