msm/hdmi/hdmi_phy_8x60.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Red Hat
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006
0007 #include <linux/delay.h>
0008
0009 #include "hdmi.h"
0010
0011 static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
0012         unsigned long int pixclock)
0013 {
0014     /* De-serializer delay D/C for non-lbk mode: */
0015     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG0,
0016                HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
0017
0018     if (pixclock == 27000000) {
0019         /* video_format == HDMI_VFRMT_720x480p60_16_9 */
0020         hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
0021                    HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
0022                    HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
0023     } else {
0024         hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
0025                    HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
0026                    HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
0027     }
0028
0029     /* No matter what, start from the power down mode: */
0030     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0031                HDMI_8x60_PHY_REG2_PD_PWRGEN |
0032                HDMI_8x60_PHY_REG2_PD_PLL |
0033                HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
0034                HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
0035                HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
0036                HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
0037                HDMI_8x60_PHY_REG2_PD_DESER);
0038
0039     /* Turn PowerGen on: */
0040     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0041                HDMI_8x60_PHY_REG2_PD_PLL |
0042                HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
0043                HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
0044                HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
0045                HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
0046                HDMI_8x60_PHY_REG2_PD_DESER);
0047
0048     /* Turn PLL power on: */
0049     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0050                HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
0051                HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
0052                HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
0053                HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
0054                HDMI_8x60_PHY_REG2_PD_DESER);
0055
0056     /* Write to HIGH after PLL power down de-assert: */
0057     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3,
0058                HDMI_8x60_PHY_REG3_PLL_ENABLE);
0059
0060     /* ASIC power on; PHY REG9 = 0 */
0061     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
0062
0063     /* Enable PLL lock detect, PLL lock det will go high after lock
0064      * Enable the re-time logic
0065      */
0066     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
0067                HDMI_8x60_PHY_REG12_RETIMING_EN |
0068                HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
0069
0070     /* Drivers are on: */
0071     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0072                HDMI_8x60_PHY_REG2_PD_DESER);
0073
0074     /* If the RX detector is needed: */
0075     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0076                HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
0077                HDMI_8x60_PHY_REG2_PD_DESER);
0078
0079     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG4, 0);
0080     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG5, 0);
0081     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG6, 0);
0082     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG7, 0);
0083     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG8, 0);
0084     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
0085     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG10, 0);
0086     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG11, 0);
0087
0088     /* If we want to use lock enable based on counting: */
0089     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
0090                HDMI_8x60_PHY_REG12_RETIMING_EN |
0091                HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
0092                HDMI_8x60_PHY_REG12_FORCE_LOCK);
0093 }
0094
0095 static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
0096 {
0097     /* Assert RESET PHY from controller */
0098     hdmi_phy_write(phy, REG_HDMI_PHY_CTRL,
0099                HDMI_PHY_CTRL_SW_RESET);
0100     udelay(10);
0101     /* De-assert RESET PHY from controller */
0102     hdmi_phy_write(phy, REG_HDMI_PHY_CTRL, 0);
0103     /* Turn off Driver */
0104     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0105                HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
0106                HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
0107                HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
0108                HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
0109                HDMI_8x60_PHY_REG2_PD_DESER);
0110     udelay(10);
0111     /* Disable PLL */
0112     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3, 0);
0113     /* Power down PHY, but keep RX-sense: */
0114     hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
0115                HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
0116                HDMI_8x60_PHY_REG2_PD_PWRGEN |
0117                HDMI_8x60_PHY_REG2_PD_PLL |
0118                HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
0119                HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
0120                HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
0121                HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
0122                HDMI_8x60_PHY_REG2_PD_DESER);
0123 }
0124
0125 static const char * const hdmi_phy_8x60_reg_names[] = {
0126     "core-vdda",
0127 };
0128
0129 static const char * const hdmi_phy_8x60_clk_names[] = {
0130     "slave_iface",
0131 };
0132
0133 const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
0134     .type = MSM_HDMI_PHY_8x60,
0135     .powerup = hdmi_phy_8x60_powerup,
0136     .powerdown = hdmi_phy_8x60_powerdown,
0137     .reg_names = hdmi_phy_8x60_reg_names,
0138     .num_regs = ARRAY_SIZE(hdmi_phy_8x60_reg_names),
0139     .clk_names = hdmi_phy_8x60_clk_names,
0140     .num_clks = ARRAY_SIZE(hdmi_phy_8x60_clk_names),
0141 };