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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
0003  */
0004 
0005 #include "hdmi.h"
0006 #include <linux/qcom_scm.h>
0007 
0008 #define HDCP_REG_ENABLE 0x01
0009 #define HDCP_REG_DISABLE 0x00
0010 #define HDCP_PORT_ADDR 0x74
0011 
0012 #define HDCP_INT_STATUS_MASK ( \
0013         HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT | \
0014         HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT | \
0015         HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT | \
0016         HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT)
0017 
0018 #define AUTH_WORK_RETRIES_TIME 100
0019 #define AUTH_RETRIES_TIME 30
0020 
0021 /* QFPROM Registers for HDMI/HDCP */
0022 #define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB  0x000000F8
0023 #define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB  0x000000FC
0024 #define HDCP_KSV_LSB                     0x000060D8
0025 #define HDCP_KSV_MSB                     0x000060DC
0026 
0027 enum DS_TYPE {  /* type of downstream device */
0028     DS_UNKNOWN,
0029     DS_RECEIVER,
0030     DS_REPEATER,
0031 };
0032 
0033 enum hdmi_hdcp_state {
0034     HDCP_STATE_NO_AKSV,
0035     HDCP_STATE_INACTIVE,
0036     HDCP_STATE_AUTHENTICATING,
0037     HDCP_STATE_AUTHENTICATED,
0038     HDCP_STATE_AUTH_FAILED
0039 };
0040 
0041 struct hdmi_hdcp_reg_data {
0042     u32 reg_id;
0043     u32 off;
0044     char *name;
0045     u32 reg_val;
0046 };
0047 
0048 struct hdmi_hdcp_ctrl {
0049     struct hdmi *hdmi;
0050     u32 auth_retries;
0051     bool tz_hdcp;
0052     enum hdmi_hdcp_state hdcp_state;
0053     struct work_struct hdcp_auth_work;
0054     struct work_struct hdcp_reauth_work;
0055 
0056 #define AUTH_ABORT_EV 1
0057 #define AUTH_RESULT_RDY_EV 2
0058     unsigned long auth_event;
0059     wait_queue_head_t auth_event_queue;
0060 
0061     u32 ksv_fifo_w_index;
0062     /*
0063      * store aksv from qfprom
0064      */
0065     u32 aksv_lsb;
0066     u32 aksv_msb;
0067     bool aksv_valid;
0068     u32 ds_type;
0069     u32 bksv_lsb;
0070     u32 bksv_msb;
0071     u8 dev_count;
0072     u8 depth;
0073     u8 ksv_list[5 * 127];
0074     bool max_cascade_exceeded;
0075     bool max_dev_exceeded;
0076 };
0077 
0078 static int msm_hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset,
0079     u8 *data, u16 data_len)
0080 {
0081     int rc;
0082     int retry = 5;
0083     struct i2c_msg msgs[] = {
0084         {
0085             .addr   = addr >> 1,
0086             .flags  = 0,
0087             .len    = 1,
0088             .buf    = &offset,
0089         }, {
0090             .addr   = addr >> 1,
0091             .flags  = I2C_M_RD,
0092             .len    = data_len,
0093             .buf    = data,
0094         }
0095     };
0096 
0097     DBG("Start DDC read");
0098 retry:
0099     rc = i2c_transfer(hdmi->i2c, msgs, 2);
0100 
0101     retry--;
0102     if (rc == 2)
0103         rc = 0;
0104     else if (retry > 0)
0105         goto retry;
0106     else
0107         rc = -EIO;
0108 
0109     DBG("End DDC read %d", rc);
0110 
0111     return rc;
0112 }
0113 
0114 #define HDCP_DDC_WRITE_MAX_BYTE_NUM 32
0115 
0116 static int msm_hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset,
0117     u8 *data, u16 data_len)
0118 {
0119     int rc;
0120     int retry = 10;
0121     u8 buf[HDCP_DDC_WRITE_MAX_BYTE_NUM];
0122     struct i2c_msg msgs[] = {
0123         {
0124             .addr   = addr >> 1,
0125             .flags  = 0,
0126             .len    = 1,
0127         }
0128     };
0129 
0130     DBG("Start DDC write");
0131     if (data_len > (HDCP_DDC_WRITE_MAX_BYTE_NUM - 1)) {
0132         pr_err("%s: write size too big\n", __func__);
0133         return -ERANGE;
0134     }
0135 
0136     buf[0] = offset;
0137     memcpy(&buf[1], data, data_len);
0138     msgs[0].buf = buf;
0139     msgs[0].len = data_len + 1;
0140 retry:
0141     rc = i2c_transfer(hdmi->i2c, msgs, 1);
0142 
0143     retry--;
0144     if (rc == 1)
0145         rc = 0;
0146     else if (retry > 0)
0147         goto retry;
0148     else
0149         rc = -EIO;
0150 
0151     DBG("End DDC write %d", rc);
0152 
0153     return rc;
0154 }
0155 
0156 static int msm_hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg,
0157     u32 *pdata, u32 count)
0158 {
0159     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0160     struct qcom_scm_hdcp_req scm_buf[QCOM_SCM_HDCP_MAX_REQ_CNT];
0161     u32 resp, phy_addr, idx = 0;
0162     int i, ret = 0;
0163 
0164     WARN_ON(!pdata || !preg || (count == 0));
0165 
0166     if (hdcp_ctrl->tz_hdcp) {
0167         phy_addr = (u32)hdmi->mmio_phy_addr;
0168 
0169         while (count) {
0170             memset(scm_buf, 0, sizeof(scm_buf));
0171             for (i = 0; i < count && i < QCOM_SCM_HDCP_MAX_REQ_CNT;
0172                 i++) {
0173                 scm_buf[i].addr = phy_addr + preg[idx];
0174                 scm_buf[i].val  = pdata[idx];
0175                 idx++;
0176             }
0177             ret = qcom_scm_hdcp_req(scm_buf, i, &resp);
0178 
0179             if (ret || resp) {
0180                 pr_err("%s: error: scm_call ret=%d resp=%u\n",
0181                     __func__, ret, resp);
0182                 ret = -EINVAL;
0183                 break;
0184             }
0185 
0186             count -= i;
0187         }
0188     } else {
0189         for (i = 0; i < count; i++)
0190             hdmi_write(hdmi, preg[i], pdata[i]);
0191     }
0192 
0193     return ret;
0194 }
0195 
0196 void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0197 {
0198     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0199     u32 reg_val, hdcp_int_status;
0200     unsigned long flags;
0201 
0202     spin_lock_irqsave(&hdmi->reg_lock, flags);
0203     reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL);
0204     hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK;
0205     if (!hdcp_int_status) {
0206         spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0207         return;
0208     }
0209     /* Clear Interrupts */
0210     reg_val |= hdcp_int_status << 1;
0211     /* Clear AUTH_FAIL_INFO as well */
0212     if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT)
0213         reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK;
0214     hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val);
0215     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0216 
0217     DBG("hdcp irq %x", hdcp_int_status);
0218 
0219     if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT) {
0220         pr_info("%s:AUTH_SUCCESS_INT received\n", __func__);
0221         if (HDCP_STATE_AUTHENTICATING == hdcp_ctrl->hdcp_state) {
0222             set_bit(AUTH_RESULT_RDY_EV, &hdcp_ctrl->auth_event);
0223             wake_up_all(&hdcp_ctrl->auth_event_queue);
0224         }
0225     }
0226 
0227     if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT) {
0228         reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
0229         pr_info("%s: AUTH_FAIL_INT rcvd, LINK0_STATUS=0x%08x\n",
0230             __func__, reg_val);
0231         if (HDCP_STATE_AUTHENTICATED == hdcp_ctrl->hdcp_state)
0232             queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work);
0233         else if (HDCP_STATE_AUTHENTICATING ==
0234                 hdcp_ctrl->hdcp_state) {
0235             set_bit(AUTH_RESULT_RDY_EV, &hdcp_ctrl->auth_event);
0236             wake_up_all(&hdcp_ctrl->auth_event_queue);
0237         }
0238     }
0239 }
0240 
0241 static int msm_hdmi_hdcp_msleep(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 ms, u32 ev)
0242 {
0243     int rc;
0244 
0245     rc = wait_event_timeout(hdcp_ctrl->auth_event_queue,
0246         !!test_bit(ev, &hdcp_ctrl->auth_event),
0247         msecs_to_jiffies(ms));
0248     if (rc) {
0249         pr_info("%s: msleep is canceled by event %d\n",
0250                 __func__, ev);
0251         clear_bit(ev, &hdcp_ctrl->auth_event);
0252         return -ECANCELED;
0253     }
0254 
0255     return 0;
0256 }
0257 
0258 static int msm_hdmi_hdcp_read_validate_aksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0259 {
0260     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0261 
0262     /* Fetch aksv from QFPROM, this info should be public. */
0263     hdcp_ctrl->aksv_lsb = hdmi_qfprom_read(hdmi, HDCP_KSV_LSB);
0264     hdcp_ctrl->aksv_msb = hdmi_qfprom_read(hdmi, HDCP_KSV_MSB);
0265 
0266     /* check there are 20 ones in AKSV */
0267     if ((hweight32(hdcp_ctrl->aksv_lsb) + hweight32(hdcp_ctrl->aksv_msb))
0268             != 20) {
0269         pr_err("%s: AKSV QFPROM doesn't have 20 1's, 20 0's\n",
0270             __func__);
0271         pr_err("%s: QFPROM AKSV chk failed (AKSV=%02x%08x)\n",
0272             __func__, hdcp_ctrl->aksv_msb,
0273             hdcp_ctrl->aksv_lsb);
0274         return -EINVAL;
0275     }
0276     DBG("AKSV=%02x%08x", hdcp_ctrl->aksv_msb, hdcp_ctrl->aksv_lsb);
0277 
0278     return 0;
0279 }
0280 
0281 static int msm_reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0282 {
0283     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0284     u32 reg_val, failure, nack0;
0285     int rc = 0;
0286 
0287     /* Check for any DDC transfer failures */
0288     reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);
0289     failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED;
0290     nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0;
0291     DBG("HDCP_DDC_STATUS=0x%x, FAIL=%d, NACK0=%d",
0292         reg_val, failure, nack0);
0293 
0294     if (failure) {
0295         /*
0296          * Indicates that the last HDCP HW DDC transfer failed.
0297          * This occurs when a transfer is attempted with HDCP DDC
0298          * disabled (HDCP_DDC_DISABLE=1) or the number of retries
0299          * matches HDCP_DDC_RETRY_CNT.
0300          * Failure occurred,  let's clear it.
0301          */
0302         DBG("DDC failure detected");
0303 
0304         /* First, Disable DDC */
0305         hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_0,
0306             HDMI_HDCP_DDC_CTRL_0_DISABLE);
0307 
0308         /* ACK the Failure to Clear it */
0309         reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1);
0310         reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK;
0311         hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val);
0312 
0313         /* Check if the FAILURE got Cleared */
0314         reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);
0315         if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED)
0316             pr_info("%s: Unable to clear HDCP DDC Failure\n",
0317                 __func__);
0318 
0319         /* Re-Enable HDCP DDC */
0320         hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_0, 0);
0321     }
0322 
0323     if (nack0) {
0324         DBG("Before: HDMI_DDC_SW_STATUS=0x%08x",
0325             hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS));
0326         /* Reset HDMI DDC software status */
0327         reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
0328         reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET;
0329         hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
0330 
0331         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
0332 
0333         reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
0334         reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET;
0335         hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
0336 
0337         /* Reset HDMI DDC Controller */
0338         reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
0339         reg_val |= HDMI_DDC_CTRL_SOFT_RESET;
0340         hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
0341 
0342         /* If previous msleep is aborted, skip this msleep */
0343         if (!rc)
0344             rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
0345 
0346         reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
0347         reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET;
0348         hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
0349         DBG("After: HDMI_DDC_SW_STATUS=0x%08x",
0350             hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS));
0351     }
0352 
0353     return rc;
0354 }
0355 
0356 static int msm_hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0357 {
0358     int rc;
0359     u32 hdcp_ddc_status, ddc_hw_status;
0360     u32 xfer_done, xfer_req, hw_done;
0361     bool hw_not_ready;
0362     u32 timeout_count;
0363     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0364 
0365     if (hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS) == 0)
0366         return 0;
0367 
0368     /* Wait to be clean on DDC HW engine */
0369     timeout_count = 100;
0370     do {
0371         hdcp_ddc_status = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);
0372         ddc_hw_status = hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS);
0373 
0374         xfer_done = hdcp_ddc_status & HDMI_HDCP_DDC_STATUS_XFER_DONE;
0375         xfer_req = hdcp_ddc_status & HDMI_HDCP_DDC_STATUS_XFER_REQ;
0376         hw_done = ddc_hw_status & HDMI_DDC_HW_STATUS_DONE;
0377         hw_not_ready = !xfer_done || xfer_req || !hw_done;
0378 
0379         if (hw_not_ready)
0380             break;
0381 
0382         timeout_count--;
0383         if (!timeout_count) {
0384             pr_warn("%s: hw_ddc_clean failed\n", __func__);
0385             return -ETIMEDOUT;
0386         }
0387 
0388         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
0389         if (rc)
0390             return rc;
0391     } while (1);
0392 
0393     return 0;
0394 }
0395 
0396 static void msm_hdmi_hdcp_reauth_work(struct work_struct *work)
0397 {
0398     struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work,
0399         struct hdmi_hdcp_ctrl, hdcp_reauth_work);
0400     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0401     unsigned long flags;
0402     u32 reg_val;
0403 
0404     DBG("HDCP REAUTH WORK");
0405     /*
0406      * Disable HPD circuitry.
0407      * This is needed to reset the HDCP cipher engine so that when we
0408      * attempt a re-authentication, HW would clear the AN0_READY and
0409      * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register
0410      */
0411     spin_lock_irqsave(&hdmi->reg_lock, flags);
0412     reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
0413     reg_val &= ~HDMI_HPD_CTRL_ENABLE;
0414     hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
0415 
0416     /* Disable HDCP interrupts */
0417     hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0);
0418     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0419 
0420     hdmi_write(hdmi, REG_HDMI_HDCP_RESET,
0421         HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE);
0422 
0423     /* Wait to be clean on DDC HW engine */
0424     if (msm_hdmi_hdcp_hw_ddc_clean(hdcp_ctrl)) {
0425         pr_info("%s: reauth work aborted\n", __func__);
0426         return;
0427     }
0428 
0429     /* Disable encryption and disable the HDCP block */
0430     hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0);
0431 
0432     /* Enable HPD circuitry */
0433     spin_lock_irqsave(&hdmi->reg_lock, flags);
0434     reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
0435     reg_val |= HDMI_HPD_CTRL_ENABLE;
0436     hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
0437     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0438 
0439     /*
0440      * Only retry defined times then abort current authenticating process
0441      */
0442     if (++hdcp_ctrl->auth_retries == AUTH_RETRIES_TIME) {
0443         hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE;
0444         hdcp_ctrl->auth_retries = 0;
0445         pr_info("%s: abort reauthentication!\n", __func__);
0446 
0447         return;
0448     }
0449 
0450     DBG("Queue AUTH WORK");
0451     hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING;
0452     queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work);
0453 }
0454 
0455 static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0456 {
0457     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0458     u32 link0_status;
0459     u32 reg_val;
0460     unsigned long flags;
0461     int rc;
0462 
0463     if (!hdcp_ctrl->aksv_valid) {
0464         rc = msm_hdmi_hdcp_read_validate_aksv(hdcp_ctrl);
0465         if (rc) {
0466             pr_err("%s: ASKV validation failed\n", __func__);
0467             hdcp_ctrl->hdcp_state = HDCP_STATE_NO_AKSV;
0468             return -ENOTSUPP;
0469         }
0470         hdcp_ctrl->aksv_valid = true;
0471     }
0472 
0473     spin_lock_irqsave(&hdmi->reg_lock, flags);
0474     /* disable HDMI Encrypt */
0475     reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
0476     reg_val &= ~HDMI_CTRL_ENCRYPTED;
0477     hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
0478 
0479     /* Enabling Software DDC */
0480     reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION);
0481     reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION;
0482     hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val);
0483     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0484 
0485     /*
0486      * Write AKSV read from QFPROM to the HDCP registers.
0487      * This step is needed for HDCP authentication and must be
0488      * written before enabling HDCP.
0489      */
0490     hdmi_write(hdmi, REG_HDMI_HDCP_SW_LOWER_AKSV, hdcp_ctrl->aksv_lsb);
0491     hdmi_write(hdmi, REG_HDMI_HDCP_SW_UPPER_AKSV, hdcp_ctrl->aksv_msb);
0492 
0493     /*
0494      * HDCP setup prior to enabling HDCP_CTRL.
0495      * Setup seed values for random number An.
0496      */
0497     hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL0, 0xB1FFB0FF);
0498     hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL1, 0xF00DFACE);
0499 
0500     /* Disable the RngCipher state */
0501     reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL);
0502     reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER;
0503     hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val);
0504     DBG("HDCP_DEBUG_CTRL=0x%08x",
0505         hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL));
0506 
0507     /*
0508      * Ensure that all register writes are completed before
0509      * enabling HDCP cipher
0510      */
0511     wmb();
0512 
0513     /*
0514      * Enable HDCP
0515      * This needs to be done as early as possible in order for the
0516      * hardware to make An available to read
0517      */
0518     hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, HDMI_HDCP_CTRL_ENABLE);
0519 
0520     /*
0521      * If we had stale values for the An ready bit, it should most
0522      * likely be cleared now after enabling HDCP cipher
0523      */
0524     link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
0525     DBG("After enabling HDCP Link0_Status=0x%08x", link0_status);
0526     if (!(link0_status &
0527         (HDMI_HDCP_LINK0_STATUS_AN_0_READY |
0528         HDMI_HDCP_LINK0_STATUS_AN_1_READY)))
0529         DBG("An not ready after enabling HDCP");
0530 
0531     /* Clear any DDC failures from previous tries before enable HDCP*/
0532     rc = msm_reset_hdcp_ddc_failures(hdcp_ctrl);
0533 
0534     return rc;
0535 }
0536 
0537 static void msm_hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0538 {
0539     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0540     u32 reg_val;
0541     unsigned long flags;
0542 
0543     DBG("hdcp auth failed, queue reauth work");
0544     /* clear HDMI Encrypt */
0545     spin_lock_irqsave(&hdmi->reg_lock, flags);
0546     reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
0547     reg_val &= ~HDMI_CTRL_ENCRYPTED;
0548     hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
0549     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0550 
0551     hdcp_ctrl->hdcp_state = HDCP_STATE_AUTH_FAILED;
0552     queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work);
0553 }
0554 
0555 static void msm_hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0556 {
0557     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0558     u32 reg_val;
0559     unsigned long flags;
0560 
0561     /*
0562      * Disable software DDC before going into part3 to make sure
0563      * there is no Arbitration between software and hardware for DDC
0564      */
0565     spin_lock_irqsave(&hdmi->reg_lock, flags);
0566     reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION);
0567     reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION;
0568     hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val);
0569     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0570 
0571     /* enable HDMI Encrypt */
0572     spin_lock_irqsave(&hdmi->reg_lock, flags);
0573     reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
0574     reg_val |= HDMI_CTRL_ENCRYPTED;
0575     hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
0576     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0577 
0578     hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATED;
0579     hdcp_ctrl->auth_retries = 0;
0580 }
0581 
0582 /*
0583  * hdcp authenticating part 1
0584  * Wait Key/An ready
0585  * Read BCAPS from sink
0586  * Write BCAPS and AKSV into HDCP engine
0587  * Write An and AKSV to sink
0588  * Read BKSV from sink and write into HDCP engine
0589  */
0590 static int msm_hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0591 {
0592     int rc;
0593     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0594     u32 link0_status, keys_state;
0595     u32 timeout_count;
0596     bool an_ready;
0597 
0598     /* Wait for HDCP keys to be checked and validated */
0599     timeout_count = 100;
0600     do {
0601         link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
0602         keys_state = (link0_status >> 28) & 0x7;
0603         if (keys_state == HDCP_KEYS_STATE_VALID)
0604             break;
0605 
0606         DBG("Keys not ready(%d). s=%d, l0=%0x08x",
0607             timeout_count, keys_state, link0_status);
0608 
0609         timeout_count--;
0610         if (!timeout_count) {
0611             pr_err("%s: Wait key state timedout", __func__);
0612             return -ETIMEDOUT;
0613         }
0614 
0615         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
0616         if (rc)
0617             return rc;
0618     } while (1);
0619 
0620     timeout_count = 100;
0621     do {
0622         link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
0623         an_ready = (link0_status & HDMI_HDCP_LINK0_STATUS_AN_0_READY)
0624             && (link0_status & HDMI_HDCP_LINK0_STATUS_AN_1_READY);
0625         if (an_ready)
0626             break;
0627 
0628         DBG("An not ready(%d). l0_status=0x%08x",
0629             timeout_count, link0_status);
0630 
0631         timeout_count--;
0632         if (!timeout_count) {
0633             pr_err("%s: Wait An timedout", __func__);
0634             return -ETIMEDOUT;
0635         }
0636 
0637         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
0638         if (rc)
0639             return rc;
0640     } while (1);
0641 
0642     return 0;
0643 }
0644 
0645 static int msm_hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0646 {
0647     int rc = 0;
0648     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0649     u32 link0_aksv_0, link0_aksv_1;
0650     u32 link0_an[2];
0651     u8 aksv[5];
0652 
0653     /* Read An0 and An1 */
0654     link0_an[0] = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA5);
0655     link0_an[1] = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA6);
0656 
0657     /* Read AKSV */
0658     link0_aksv_0 = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA3);
0659     link0_aksv_1 = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4);
0660 
0661     DBG("Link ASKV=%08x%08x", link0_aksv_0, link0_aksv_1);
0662     /* Copy An and AKSV to byte arrays for transmission */
0663     aksv[0] =  link0_aksv_0        & 0xFF;
0664     aksv[1] = (link0_aksv_0 >> 8)  & 0xFF;
0665     aksv[2] = (link0_aksv_0 >> 16) & 0xFF;
0666     aksv[3] = (link0_aksv_0 >> 24) & 0xFF;
0667     aksv[4] =  link0_aksv_1        & 0xFF;
0668 
0669     /* Write An to offset 0x18 */
0670     rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x18, (u8 *)link0_an,
0671         (u16)sizeof(link0_an));
0672     if (rc) {
0673         pr_err("%s:An write failed\n", __func__);
0674         return rc;
0675     }
0676     DBG("Link0-An=%08x%08x", link0_an[0], link0_an[1]);
0677 
0678     /* Write AKSV to offset 0x10 */
0679     rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x10, aksv, 5);
0680     if (rc) {
0681         pr_err("%s:AKSV write failed\n", __func__);
0682         return rc;
0683     }
0684     DBG("Link0-AKSV=%02x%08x", link0_aksv_1 & 0xFF, link0_aksv_0);
0685 
0686     return 0;
0687 }
0688 
0689 static int msm_hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0690 {
0691     int rc = 0;
0692     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0693     u8 bksv[5];
0694     u32 reg[2], data[2];
0695 
0696     /* Read BKSV at offset 0x00 */
0697     rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x00, bksv, 5);
0698     if (rc) {
0699         pr_err("%s:BKSV read failed\n", __func__);
0700         return rc;
0701     }
0702 
0703     hdcp_ctrl->bksv_lsb = bksv[0] | (bksv[1] << 8) |
0704         (bksv[2] << 16) | (bksv[3] << 24);
0705     hdcp_ctrl->bksv_msb = bksv[4];
0706     DBG(":BKSV=%02x%08x", hdcp_ctrl->bksv_msb, hdcp_ctrl->bksv_lsb);
0707 
0708     /* check there are 20 ones in BKSV */
0709     if ((hweight32(hdcp_ctrl->bksv_lsb) + hweight32(hdcp_ctrl->bksv_msb))
0710             != 20) {
0711         pr_err(": BKSV doesn't have 20 1's and 20 0's\n");
0712         pr_err(": BKSV chk fail. BKSV=%02x%02x%02x%02x%02x\n",
0713             bksv[4], bksv[3], bksv[2], bksv[1], bksv[0]);
0714         return -EINVAL;
0715     }
0716 
0717     /* Write BKSV read from sink to HDCP registers */
0718     reg[0] = REG_HDMI_HDCP_RCVPORT_DATA0;
0719     data[0] = hdcp_ctrl->bksv_lsb;
0720     reg[1] = REG_HDMI_HDCP_RCVPORT_DATA1;
0721     data[1] = hdcp_ctrl->bksv_msb;
0722     rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2);
0723 
0724     return rc;
0725 }
0726 
0727 static int msm_hdmi_hdcp_recv_bcaps(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0728 {
0729     int rc = 0;
0730     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0731     u32 reg, data;
0732     u8 bcaps;
0733 
0734     rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1);
0735     if (rc) {
0736         pr_err("%s:BCAPS read failed\n", __func__);
0737         return rc;
0738     }
0739     DBG("BCAPS=%02x", bcaps);
0740 
0741     /* receiver (0), repeater (1) */
0742     hdcp_ctrl->ds_type = (bcaps & BIT(6)) ? DS_REPEATER : DS_RECEIVER;
0743 
0744     /* Write BCAPS to the hardware */
0745     reg = REG_HDMI_HDCP_RCVPORT_DATA12;
0746     data = (u32)bcaps;
0747     rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
0748 
0749     return rc;
0750 }
0751 
0752 static int msm_hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0753 {
0754     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0755     unsigned long flags;
0756     int rc;
0757 
0758     /* Wait for AKSV key and An ready */
0759     rc = msm_hdmi_hdcp_wait_key_an_ready(hdcp_ctrl);
0760     if (rc) {
0761         pr_err("%s: wait key and an ready failed\n", __func__);
0762         return rc;
0763     }
0764 
0765     /* Read BCAPS and send to HDCP engine */
0766     rc = msm_hdmi_hdcp_recv_bcaps(hdcp_ctrl);
0767     if (rc) {
0768         pr_err("%s: read bcaps error, abort\n", __func__);
0769         return rc;
0770     }
0771 
0772     /*
0773      * 1.1_Features turned off by default.
0774      * No need to write AInfo since 1.1_Features is disabled.
0775      */
0776     hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4, 0);
0777 
0778     /* Send AKSV and An to sink */
0779     rc = msm_hdmi_hdcp_send_aksv_an(hdcp_ctrl);
0780     if (rc) {
0781         pr_err("%s:An/Aksv write failed\n", __func__);
0782         return rc;
0783     }
0784 
0785     /* Read BKSV and send to HDCP engine*/
0786     rc = msm_hdmi_hdcp_recv_bksv(hdcp_ctrl);
0787     if (rc) {
0788         pr_err("%s:BKSV Process failed\n", __func__);
0789         return rc;
0790     }
0791 
0792     /* Enable HDCP interrupts and ack/clear any stale interrupts */
0793     spin_lock_irqsave(&hdmi->reg_lock, flags);
0794     hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL,
0795         HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK |
0796         HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK |
0797         HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK |
0798         HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK |
0799         HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK);
0800     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
0801 
0802     return 0;
0803 }
0804 
0805 /* read R0' from sink and pass it to HDCP engine */
0806 static int msm_hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0807 {
0808     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0809     int rc = 0;
0810     u8 buf[2];
0811 
0812     /*
0813      * HDCP Compliance Test case 1A-01:
0814      * Wait here at least 100ms before reading R0'
0815      */
0816     rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 125, AUTH_ABORT_EV);
0817     if (rc)
0818         return rc;
0819 
0820     /* Read R0' at offset 0x08 */
0821     rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x08, buf, 2);
0822     if (rc) {
0823         pr_err("%s:R0' read failed\n", __func__);
0824         return rc;
0825     }
0826     DBG("R0'=%02x%02x", buf[1], buf[0]);
0827 
0828     /* Write R0' to HDCP registers and check to see if it is a match */
0829     hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA2_0,
0830         (((u32)buf[1]) << 8) | buf[0]);
0831 
0832     return 0;
0833 }
0834 
0835 /* Wait for authenticating result: R0/R0' are matched or not */
0836 static int msm_hdmi_hdcp_auth_part1_verify_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0837 {
0838     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0839     u32 link0_status;
0840     int rc;
0841 
0842     /* wait for hdcp irq, 10 sec should be long enough */
0843     rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 10000, AUTH_RESULT_RDY_EV);
0844     if (!rc) {
0845         pr_err("%s: Wait Auth IRQ timeout\n", __func__);
0846         return -ETIMEDOUT;
0847     }
0848 
0849     link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
0850     if (!(link0_status & HDMI_HDCP_LINK0_STATUS_RI_MATCHES)) {
0851         pr_err("%s: Authentication Part I failed\n", __func__);
0852         return -EINVAL;
0853     }
0854 
0855     /* Enable HDCP Encryption */
0856     hdmi_write(hdmi, REG_HDMI_HDCP_CTRL,
0857         HDMI_HDCP_CTRL_ENABLE |
0858         HDMI_HDCP_CTRL_ENCRYPTION_ENABLE);
0859 
0860     return 0;
0861 }
0862 
0863 static int msm_hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl,
0864     u16 *pbstatus)
0865 {
0866     int rc;
0867     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0868     bool max_devs_exceeded = false, max_cascade_exceeded = false;
0869     u32 repeater_cascade_depth = 0, down_stream_devices = 0;
0870     u16 bstatus;
0871     u8 buf[2];
0872 
0873     /* Read BSTATUS at offset 0x41 */
0874     rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x41, buf, 2);
0875     if (rc) {
0876         pr_err("%s: BSTATUS read failed\n", __func__);
0877         goto error;
0878     }
0879     *pbstatus = bstatus = (buf[1] << 8) | buf[0];
0880 
0881 
0882     down_stream_devices = bstatus & 0x7F;
0883     repeater_cascade_depth = (bstatus >> 8) & 0x7;
0884     max_devs_exceeded = (bstatus & BIT(7)) ? true : false;
0885     max_cascade_exceeded = (bstatus & BIT(11)) ? true : false;
0886 
0887     if (down_stream_devices == 0) {
0888         /*
0889          * If no downstream devices are attached to the repeater
0890          * then part II fails.
0891          * todo: The other approach would be to continue PART II.
0892          */
0893         pr_err("%s: No downstream devices\n", __func__);
0894         rc = -EINVAL;
0895         goto error;
0896     }
0897 
0898     /*
0899      * HDCP Compliance 1B-05:
0900      * Check if no. of devices connected to repeater
0901      * exceed max_devices_connected from bit 7 of Bstatus.
0902      */
0903     if (max_devs_exceeded) {
0904         pr_err("%s: no. of devs connected exceeds max allowed",
0905             __func__);
0906         rc = -EINVAL;
0907         goto error;
0908     }
0909 
0910     /*
0911      * HDCP Compliance 1B-06:
0912      * Check if no. of cascade connected to repeater
0913      * exceed max_cascade_connected from bit 11 of Bstatus.
0914      */
0915     if (max_cascade_exceeded) {
0916         pr_err("%s: no. of cascade conn exceeds max allowed",
0917             __func__);
0918         rc = -EINVAL;
0919         goto error;
0920     }
0921 
0922 error:
0923     hdcp_ctrl->dev_count = down_stream_devices;
0924     hdcp_ctrl->max_cascade_exceeded = max_cascade_exceeded;
0925     hdcp_ctrl->max_dev_exceeded = max_devs_exceeded;
0926     hdcp_ctrl->depth = repeater_cascade_depth;
0927     return rc;
0928 }
0929 
0930 static int msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
0931     struct hdmi_hdcp_ctrl *hdcp_ctrl)
0932 {
0933     int rc;
0934     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0935     u32 reg, data;
0936     u32 timeout_count;
0937     u16 bstatus;
0938     u8 bcaps;
0939 
0940     /*
0941      * Wait until READY bit is set in BCAPS, as per HDCP specifications
0942      * maximum permitted time to check for READY bit is five seconds.
0943      */
0944     timeout_count = 100;
0945     do {
0946         /* Read BCAPS at offset 0x40 */
0947         rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1);
0948         if (rc) {
0949             pr_err("%s: BCAPS read failed\n", __func__);
0950             return rc;
0951         }
0952 
0953         if (bcaps & BIT(5))
0954             break;
0955 
0956         timeout_count--;
0957         if (!timeout_count) {
0958             pr_err("%s: Wait KSV fifo ready timedout", __func__);
0959             return -ETIMEDOUT;
0960         }
0961 
0962         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
0963         if (rc)
0964             return rc;
0965     } while (1);
0966 
0967     rc = msm_hdmi_hdcp_recv_check_bstatus(hdcp_ctrl, &bstatus);
0968     if (rc) {
0969         pr_err("%s: bstatus error\n", __func__);
0970         return rc;
0971     }
0972 
0973     /* Write BSTATUS and BCAPS to HDCP registers */
0974     reg = REG_HDMI_HDCP_RCVPORT_DATA12;
0975     data = bcaps | (bstatus << 8);
0976     rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
0977     if (rc) {
0978         pr_err("%s: BSTATUS write failed\n", __func__);
0979         return rc;
0980     }
0981 
0982     return 0;
0983 }
0984 
0985 /*
0986  * hdcp authenticating part 2: 2nd
0987  * read ksv fifo from sink
0988  * transfer V' from sink to HDCP engine
0989  * reset SHA engine
0990  */
0991 static int msm_hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl)
0992 {
0993     struct hdmi *hdmi = hdcp_ctrl->hdmi;
0994     int rc = 0;
0995     struct hdmi_hdcp_reg_data reg_data[]  = {
0996         {REG_HDMI_HDCP_RCVPORT_DATA7,  0x20, "V' H0"},
0997         {REG_HDMI_HDCP_RCVPORT_DATA8,  0x24, "V' H1"},
0998         {REG_HDMI_HDCP_RCVPORT_DATA9,  0x28, "V' H2"},
0999         {REG_HDMI_HDCP_RCVPORT_DATA10, 0x2C, "V' H3"},
1000         {REG_HDMI_HDCP_RCVPORT_DATA11, 0x30, "V' H4"},
1001     };
1002     struct hdmi_hdcp_reg_data *rd;
1003     u32 size = ARRAY_SIZE(reg_data);
1004     u32 reg[ARRAY_SIZE(reg_data)];
1005     u32 data[ARRAY_SIZE(reg_data)];
1006     int i;
1007 
1008     for (i = 0; i < size; i++) {
1009         rd = &reg_data[i];
1010         rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR,
1011             rd->off, (u8 *)&data[i], (u16)sizeof(data[i]));
1012         if (rc) {
1013             pr_err("%s: Read %s failed\n", __func__, rd->name);
1014             goto error;
1015         }
1016 
1017         DBG("%s =%x", rd->name, data[i]);
1018         reg[i] = reg_data[i].reg_id;
1019     }
1020 
1021     rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, size);
1022 
1023 error:
1024     return rc;
1025 }
1026 
1027 static int msm_hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
1028 {
1029     int rc;
1030     struct hdmi *hdmi = hdcp_ctrl->hdmi;
1031     u32 ksv_bytes;
1032 
1033     ksv_bytes = 5 * hdcp_ctrl->dev_count;
1034 
1035     rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x43,
1036         hdcp_ctrl->ksv_list, ksv_bytes);
1037     if (rc)
1038         pr_err("%s: KSV FIFO read failed\n", __func__);
1039 
1040     return rc;
1041 }
1042 
1043 static int msm_hdmi_hdcp_reset_sha_engine(struct hdmi_hdcp_ctrl *hdcp_ctrl)
1044 {
1045     u32 reg[2], data[2];
1046     u32 rc  = 0;
1047 
1048     reg[0] = REG_HDMI_HDCP_SHA_CTRL;
1049     data[0] = HDCP_REG_ENABLE;
1050     reg[1] = REG_HDMI_HDCP_SHA_CTRL;
1051     data[1] = HDCP_REG_DISABLE;
1052 
1053     rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2);
1054 
1055     return rc;
1056 }
1057 
1058 static int msm_hdmi_hdcp_auth_part2_recv_ksv_fifo(
1059     struct hdmi_hdcp_ctrl *hdcp_ctrl)
1060 {
1061     int rc;
1062     u32 timeout_count;
1063 
1064     /*
1065      * Read KSV FIFO over DDC
1066      * Key Selection vector FIFO Used to pull downstream KSVs
1067      * from HDCP Repeaters.
1068      * All bytes (DEVICE_COUNT * 5) must be read in a single,
1069      * auto incrementing access.
1070      * All bytes read as 0x00 for HDCP Receivers that are not
1071      * HDCP Repeaters (REPEATER == 0).
1072      */
1073     timeout_count = 100;
1074     do {
1075         rc = msm_hdmi_hdcp_recv_ksv_fifo(hdcp_ctrl);
1076         if (!rc)
1077             break;
1078 
1079         timeout_count--;
1080         if (!timeout_count) {
1081             pr_err("%s: Recv ksv fifo timedout", __func__);
1082             return -ETIMEDOUT;
1083         }
1084 
1085         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 25, AUTH_ABORT_EV);
1086         if (rc)
1087             return rc;
1088     } while (1);
1089 
1090     rc = msm_hdmi_hdcp_transfer_v_h(hdcp_ctrl);
1091     if (rc) {
1092         pr_err("%s: transfer V failed\n", __func__);
1093         return rc;
1094     }
1095 
1096     /* reset SHA engine before write ksv fifo */
1097     rc = msm_hdmi_hdcp_reset_sha_engine(hdcp_ctrl);
1098     if (rc) {
1099         pr_err("%s: fail to reset sha engine\n", __func__);
1100         return rc;
1101     }
1102 
1103     return 0;
1104 }
1105 
1106 /*
1107  * Write KSV FIFO to HDCP_SHA_DATA.
1108  * This is done 1 byte at time starting with the LSB.
1109  * Once 64 bytes have been written, we need to poll for
1110  * HDCP_SHA_BLOCK_DONE before writing any further
1111  * If the last byte is written, we need to poll for
1112  * HDCP_SHA_COMP_DONE to wait until HW finish
1113  */
1114 static int msm_hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
1115 {
1116     int i;
1117     struct hdmi *hdmi = hdcp_ctrl->hdmi;
1118     u32 ksv_bytes, last_byte = 0;
1119     u8 *ksv_fifo = NULL;
1120     u32 reg_val, data, reg;
1121     u32 rc  = 0;
1122 
1123     ksv_bytes  = 5 * hdcp_ctrl->dev_count;
1124 
1125     /* Check if need to wait for HW completion */
1126     if (hdcp_ctrl->ksv_fifo_w_index) {
1127         reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS);
1128         DBG("HDCP_SHA_STATUS=%08x", reg_val);
1129         if (hdcp_ctrl->ksv_fifo_w_index == ksv_bytes) {
1130             /* check COMP_DONE if last write */
1131             if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) {
1132                 DBG("COMP_DONE");
1133                 return 0;
1134             } else {
1135                 return -EAGAIN;
1136             }
1137         } else {
1138             /* check BLOCK_DONE if not last write */
1139             if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE))
1140                 return -EAGAIN;
1141 
1142             DBG("BLOCK_DONE");
1143         }
1144     }
1145 
1146     ksv_bytes  -= hdcp_ctrl->ksv_fifo_w_index;
1147     if (ksv_bytes <= 64)
1148         last_byte = 1;
1149     else
1150         ksv_bytes = 64;
1151 
1152     ksv_fifo = hdcp_ctrl->ksv_list;
1153     ksv_fifo += hdcp_ctrl->ksv_fifo_w_index;
1154 
1155     for (i = 0; i < ksv_bytes; i++) {
1156         /* Write KSV byte and set DONE bit[0] for last byte*/
1157         reg_val = ksv_fifo[i] << 16;
1158         if ((i == (ksv_bytes - 1)) && last_byte)
1159             reg_val |= HDMI_HDCP_SHA_DATA_DONE;
1160 
1161         reg = REG_HDMI_HDCP_SHA_DATA;
1162         data = reg_val;
1163         rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
1164 
1165         if (rc)
1166             return rc;
1167     }
1168 
1169     hdcp_ctrl->ksv_fifo_w_index += ksv_bytes;
1170 
1171     /*
1172      *return -EAGAIN to notify caller to wait for COMP_DONE or BLOCK_DONE
1173      */
1174     return -EAGAIN;
1175 }
1176 
1177 /* write ksv fifo into HDCP engine */
1178 static int msm_hdmi_hdcp_auth_part2_write_ksv_fifo(
1179     struct hdmi_hdcp_ctrl *hdcp_ctrl)
1180 {
1181     int rc;
1182     u32 timeout_count;
1183 
1184     hdcp_ctrl->ksv_fifo_w_index = 0;
1185     timeout_count = 100;
1186     do {
1187         rc = msm_hdmi_hdcp_write_ksv_fifo(hdcp_ctrl);
1188         if (!rc)
1189             break;
1190 
1191         if (rc != -EAGAIN)
1192             return rc;
1193 
1194         timeout_count--;
1195         if (!timeout_count) {
1196             pr_err("%s: Write KSV fifo timedout", __func__);
1197             return -ETIMEDOUT;
1198         }
1199 
1200         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
1201         if (rc)
1202             return rc;
1203     } while (1);
1204 
1205     return 0;
1206 }
1207 
1208 static int msm_hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl)
1209 {
1210     int rc = 0;
1211     struct hdmi *hdmi = hdcp_ctrl->hdmi;
1212     u32 link0_status;
1213     u32 timeout_count = 100;
1214 
1215     do {
1216         link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
1217         if (link0_status & HDMI_HDCP_LINK0_STATUS_V_MATCHES)
1218             break;
1219 
1220         timeout_count--;
1221         if (!timeout_count) {
1222                 pr_err("%s: HDCP V Match timedout", __func__);
1223                 return -ETIMEDOUT;
1224         }
1225 
1226         rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
1227         if (rc)
1228             return rc;
1229     } while (1);
1230 
1231     return 0;
1232 }
1233 
1234 static void msm_hdmi_hdcp_auth_work(struct work_struct *work)
1235 {
1236     struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work,
1237         struct hdmi_hdcp_ctrl, hdcp_auth_work);
1238     int rc;
1239 
1240     rc = msm_hdmi_hdcp_auth_prepare(hdcp_ctrl);
1241     if (rc) {
1242         pr_err("%s: auth prepare failed %d\n", __func__, rc);
1243         goto end;
1244     }
1245 
1246     /* HDCP PartI */
1247     rc = msm_hdmi_hdcp_auth_part1_key_exchange(hdcp_ctrl);
1248     if (rc) {
1249         pr_err("%s: key exchange failed %d\n", __func__, rc);
1250         goto end;
1251     }
1252 
1253     rc = msm_hdmi_hdcp_auth_part1_recv_r0(hdcp_ctrl);
1254     if (rc) {
1255         pr_err("%s: receive r0 failed %d\n", __func__, rc);
1256         goto end;
1257     }
1258 
1259     rc = msm_hdmi_hdcp_auth_part1_verify_r0(hdcp_ctrl);
1260     if (rc) {
1261         pr_err("%s: verify r0 failed %d\n", __func__, rc);
1262         goto end;
1263     }
1264     pr_info("%s: Authentication Part I successful\n", __func__);
1265     if (hdcp_ctrl->ds_type == DS_RECEIVER)
1266         goto end;
1267 
1268     /* HDCP PartII */
1269     rc = msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(hdcp_ctrl);
1270     if (rc) {
1271         pr_err("%s: wait ksv fifo ready failed %d\n", __func__, rc);
1272         goto end;
1273     }
1274 
1275     rc = msm_hdmi_hdcp_auth_part2_recv_ksv_fifo(hdcp_ctrl);
1276     if (rc) {
1277         pr_err("%s: recv ksv fifo failed %d\n", __func__, rc);
1278         goto end;
1279     }
1280 
1281     rc = msm_hdmi_hdcp_auth_part2_write_ksv_fifo(hdcp_ctrl);
1282     if (rc) {
1283         pr_err("%s: write ksv fifo failed %d\n", __func__, rc);
1284         goto end;
1285     }
1286 
1287     rc = msm_hdmi_hdcp_auth_part2_check_v_match(hdcp_ctrl);
1288     if (rc)
1289         pr_err("%s: check v match failed %d\n", __func__, rc);
1290 
1291 end:
1292     if (rc == -ECANCELED) {
1293         pr_info("%s: hdcp authentication canceled\n", __func__);
1294     } else if (rc == -ENOTSUPP) {
1295         pr_info("%s: hdcp is not supported\n", __func__);
1296     } else if (rc) {
1297         pr_err("%s: hdcp authentication failed\n", __func__);
1298         msm_hdmi_hdcp_auth_fail(hdcp_ctrl);
1299     } else {
1300         msm_hdmi_hdcp_auth_done(hdcp_ctrl);
1301     }
1302 }
1303 
1304 void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
1305 {
1306     struct hdmi *hdmi = hdcp_ctrl->hdmi;
1307     u32 reg_val;
1308     unsigned long flags;
1309 
1310     if ((HDCP_STATE_INACTIVE != hdcp_ctrl->hdcp_state) ||
1311         (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) {
1312         DBG("still active or activating or no askv. returning");
1313         return;
1314     }
1315 
1316     /* clear HDMI Encrypt */
1317     spin_lock_irqsave(&hdmi->reg_lock, flags);
1318     reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
1319     reg_val &= ~HDMI_CTRL_ENCRYPTED;
1320     hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
1321     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
1322 
1323     hdcp_ctrl->auth_event = 0;
1324     hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING;
1325     hdcp_ctrl->auth_retries = 0;
1326     queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work);
1327 }
1328 
1329 void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
1330 {
1331     struct hdmi *hdmi = hdcp_ctrl->hdmi;
1332     unsigned long flags;
1333     u32 reg_val;
1334 
1335     if ((HDCP_STATE_INACTIVE == hdcp_ctrl->hdcp_state) ||
1336         (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) {
1337         DBG("hdcp inactive or no aksv. returning");
1338         return;
1339     }
1340 
1341     /*
1342      * Disable HPD circuitry.
1343      * This is needed to reset the HDCP cipher engine so that when we
1344      * attempt a re-authentication, HW would clear the AN0_READY and
1345      * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register
1346      */
1347     spin_lock_irqsave(&hdmi->reg_lock, flags);
1348     reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
1349     reg_val &= ~HDMI_HPD_CTRL_ENABLE;
1350     hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
1351 
1352     /*
1353      * Disable HDCP interrupts.
1354      * Also, need to set the state to inactive here so that any ongoing
1355      * reauth works will know that the HDCP session has been turned off.
1356      */
1357     hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0);
1358     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
1359 
1360     /*
1361      * Cancel any pending auth/reauth attempts.
1362      * If one is ongoing, this will wait for it to finish.
1363      * No more reauthentication attempts will be scheduled since we
1364      * set the current state to inactive.
1365      */
1366     set_bit(AUTH_ABORT_EV, &hdcp_ctrl->auth_event);
1367     wake_up_all(&hdcp_ctrl->auth_event_queue);
1368     cancel_work_sync(&hdcp_ctrl->hdcp_auth_work);
1369     cancel_work_sync(&hdcp_ctrl->hdcp_reauth_work);
1370 
1371     hdmi_write(hdmi, REG_HDMI_HDCP_RESET,
1372         HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE);
1373 
1374     /* Disable encryption and disable the HDCP block */
1375     hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0);
1376 
1377     spin_lock_irqsave(&hdmi->reg_lock, flags);
1378     reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
1379     reg_val &= ~HDMI_CTRL_ENCRYPTED;
1380     hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
1381 
1382     /* Enable HPD circuitry */
1383     reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
1384     reg_val |= HDMI_HPD_CTRL_ENABLE;
1385     hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
1386     spin_unlock_irqrestore(&hdmi->reg_lock, flags);
1387 
1388     hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE;
1389 
1390     DBG("HDCP: Off");
1391 }
1392 
1393 struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
1394 {
1395     struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL;
1396 
1397     if (!hdmi->qfprom_mmio) {
1398         pr_err("%s: HDCP is not supported without qfprom\n",
1399             __func__);
1400         return ERR_PTR(-EINVAL);
1401     }
1402 
1403     hdcp_ctrl = kzalloc(sizeof(*hdcp_ctrl), GFP_KERNEL);
1404     if (!hdcp_ctrl)
1405         return ERR_PTR(-ENOMEM);
1406 
1407     INIT_WORK(&hdcp_ctrl->hdcp_auth_work, msm_hdmi_hdcp_auth_work);
1408     INIT_WORK(&hdcp_ctrl->hdcp_reauth_work, msm_hdmi_hdcp_reauth_work);
1409     init_waitqueue_head(&hdcp_ctrl->auth_event_queue);
1410     hdcp_ctrl->hdmi = hdmi;
1411     hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE;
1412     hdcp_ctrl->aksv_valid = false;
1413 
1414     if (qcom_scm_hdcp_available())
1415         hdcp_ctrl->tz_hdcp = true;
1416     else
1417         hdcp_ctrl->tz_hdcp = false;
1418 
1419     return hdcp_ctrl;
1420 }
1421 
1422 void msm_hdmi_hdcp_destroy(struct hdmi *hdmi)
1423 {
1424     if (hdmi) {
1425         kfree(hdmi->hdcp_ctrl);
1426         hdmi->hdcp_ctrl = NULL;
1427     }
1428 }
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