dsi/phy/dsi_phy_20nm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include "dsi_phy.h"
0007 #include "dsi.xml.h"
0008 #include "dsi_phy_20nm.xml.h"
0009
0010 static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
0011         struct msm_dsi_dphy_timing *timing)
0012 {
0013     void __iomem *base = phy->base;
0014
0015     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
0016         DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
0017     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
0018         DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
0019     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
0020         DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
0021     if (timing->clk_zero & BIT(8))
0022         dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
0023             DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
0024     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
0025         DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
0026     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
0027         DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
0028     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
0029         DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
0030     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,
0031         DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
0032     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,
0033         DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
0034     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,
0035         DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
0036         DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
0037     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,
0038         DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
0039     dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,
0040         DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
0041 }
0042
0043 static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
0044 {
0045     void __iomem *base = phy->reg_base;
0046
0047     if (!enable) {
0048         dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
0049         return;
0050     }
0051
0052     if (phy->regulator_ldo_mode) {
0053         dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);
0054         return;
0055     }
0056
0057     /* non LDO mode */
0058     dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);
0059     dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);
0060     dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);
0061     dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);
0062     dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);
0063     dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);
0064     dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
0065 }
0066
0067 static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
0068                 struct msm_dsi_phy_clk_request *clk_req)
0069 {
0070     struct msm_dsi_dphy_timing *timing = &phy->timing;
0071     int i;
0072     void __iomem *base = phy->base;
0073     u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
0074     u32 val;
0075
0076     DBG("");
0077
0078     if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
0079         DRM_DEV_ERROR(&phy->pdev->dev,
0080             "%s: D-PHY timing calculation failed\n", __func__);
0081         return -EINVAL;
0082     }
0083
0084     dsi_20nm_phy_regulator_ctrl(phy, true);
0085
0086     dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
0087
0088     val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
0089     if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE)
0090         val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
0091     else
0092         val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
0093     dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
0094
0095     for (i = 0; i < 4; i++) {
0096         dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
0097                             (i >> 1) * 0x40);
0098         dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);
0099         dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);
0100         dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);
0101         dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);
0102         dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);
0103     }
0104
0105     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);
0106     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);
0107     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);
0108     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);
0109     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);
0110     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);
0111     dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);
0112
0113     dsi_20nm_dphy_set_timing(phy, timing);
0114
0115     dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);
0116
0117     dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);
0118
0119     /* make sure everything is written before enable */
0120     wmb();
0121     dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);
0122
0123     return 0;
0124 }
0125
0126 static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
0127 {
0128     dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
0129     dsi_20nm_phy_regulator_ctrl(phy, false);
0130 }
0131
0132 const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
0133     .has_phy_regulator = true,
0134     .reg_cfg = {
0135         .num = 2,
0136         .regs = {
0137             {"vddio", 100000, 100}, /* 1.8 V */
0138             {"vcca", 10000, 100},   /* 1.0 V */
0139         },
0140     },
0141     .ops = {
0142         .enable = dsi_20nm_phy_enable,
0143         .disable = dsi_20nm_phy_disable,
0144     },
0145     .io_start = { 0xfd998500, 0xfd9a0500 },
0146     .num_dsi_phy = 2,
0147 };
0148