dsi/phy/dsi_phy.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef __DSI_PHY_H__
0007 #define __DSI_PHY_H__
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/delay.h>
0011 #include <linux/regulator/consumer.h>
0012
0013 #include "dsi.h"
0014
0015 #define dsi_phy_read(offset) msm_readl((offset))
0016 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
0017 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
0018 #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
0019
0020 struct msm_dsi_phy_ops {
0021     int (*pll_init)(struct msm_dsi_phy *phy);
0022     int (*enable)(struct msm_dsi_phy *phy,
0023             struct msm_dsi_phy_clk_request *clk_req);
0024     void (*disable)(struct msm_dsi_phy *phy);
0025     void (*save_pll_state)(struct msm_dsi_phy *phy);
0026     int (*restore_pll_state)(struct msm_dsi_phy *phy);
0027     bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
0028     int (*parse_dt_properties)(struct msm_dsi_phy *phy);
0029 };
0030
0031 struct msm_dsi_phy_cfg {
0032     struct dsi_reg_config reg_cfg;
0033     struct msm_dsi_phy_ops ops;
0034
0035     unsigned long   min_pll_rate;
0036     unsigned long   max_pll_rate;
0037
0038     const resource_size_t io_start[DSI_MAX];
0039     const int num_dsi_phy;
0040     const int quirks;
0041     bool has_phy_regulator;
0042     bool has_phy_lane;
0043 };
0044
0045 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
0046 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
0047 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
0048 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
0049 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
0050 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
0051 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
0052 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
0053 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
0054 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
0055 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
0056 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
0057 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
0058
0059 struct msm_dsi_dphy_timing {
0060     u32 clk_zero;
0061     u32 clk_trail;
0062     u32 clk_prepare;
0063     u32 hs_exit;
0064     u32 hs_zero;
0065     u32 hs_prepare;
0066     u32 hs_trail;
0067     u32 hs_rqst;
0068     u32 ta_go;
0069     u32 ta_sure;
0070     u32 ta_get;
0071
0072     struct msm_dsi_phy_shared_timings shared_timings;
0073
0074     /* For PHY v2 only */
0075     u32 hs_rqst_ckln;
0076     u32 hs_prep_dly;
0077     u32 hs_prep_dly_ckln;
0078     u8 hs_halfbyte_en;
0079     u8 hs_halfbyte_en_ckln;
0080 };
0081
0082 #define DSI_BYTE_PLL_CLK        0
0083 #define DSI_PIXEL_PLL_CLK       1
0084 #define NUM_PROVIDED_CLKS       2
0085
0086 #define DSI_LANE_MAX            5
0087
0088 struct msm_dsi_phy {
0089     struct platform_device *pdev;
0090     void __iomem *base;
0091     void __iomem *pll_base;
0092     void __iomem *reg_base;
0093     void __iomem *lane_base;
0094     phys_addr_t base_size;
0095     phys_addr_t pll_size;
0096     phys_addr_t reg_size;
0097     phys_addr_t lane_size;
0098     int id;
0099
0100     struct clk *ahb_clk;
0101     struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
0102
0103     struct msm_dsi_dphy_timing timing;
0104     const struct msm_dsi_phy_cfg *cfg;
0105     void *tuning_cfg;
0106
0107     enum msm_dsi_phy_usecase usecase;
0108     bool regulator_ldo_mode;
0109     bool cphy_mode;
0110
0111     struct clk_hw *vco_hw;
0112     bool pll_on;
0113
0114     struct clk_hw_onecell_data *provided_clocks;
0115
0116     bool state_saved;
0117 };
0118
0119 /*
0120  * PHY internal functions
0121  */
0122 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
0123                  struct msm_dsi_phy_clk_request *clk_req);
0124 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
0125                 struct msm_dsi_phy_clk_request *clk_req);
0126 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
0127                 struct msm_dsi_phy_clk_request *clk_req);
0128 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
0129                 struct msm_dsi_phy_clk_request *clk_req);
0130 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
0131                 struct msm_dsi_phy_clk_request *clk_req);
0132
0133 #endif /* __DSI_PHY_H__ */