msm/dsi/mmss_cc.xml.h

0001 #ifndef MMSS_CC_XML
0002 #define MMSS_CC_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054
0055
0056 enum mmss_cc_clk {
0057     CLK = 0,
0058     PCLK = 1,
0059 };
0060
0061 #define REG_MMSS_CC_AHB                     0x00000008
0062
0063 static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
0064 {
0065     switch (idx) {
0066         case CLK: return 0x0000004c;
0067         case PCLK: return 0x00000130;
0068         default: return INVALID_IDX(idx);
0069     }
0070 }
0071 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
0072
0073 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
0074 #define MMSS_CC_CLK_CC_CLK_EN                   0x00000001
0075 #define MMSS_CC_CLK_CC_ROOT_EN                  0x00000004
0076 #define MMSS_CC_CLK_CC_MND_EN                   0x00000020
0077 #define MMSS_CC_CLK_CC_MND_MODE__MASK               0x000000c0
0078 #define MMSS_CC_CLK_CC_MND_MODE__SHIFT              6
0079 static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
0080 {
0081     return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
0082 }
0083 #define MMSS_CC_CLK_CC_PMXO_SEL__MASK               0x00000300
0084 #define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT              8
0085 static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
0086 {
0087     return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
0088 }
0089
0090 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
0091 #define MMSS_CC_CLK_MD_D__MASK                  0x000000ff
0092 #define MMSS_CC_CLK_MD_D__SHIFT                 0
0093 static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
0094 {
0095     return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
0096 }
0097 #define MMSS_CC_CLK_MD_M__MASK                  0x0000ff00
0098 #define MMSS_CC_CLK_MD_M__SHIFT                 8
0099 static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
0100 {
0101     return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
0102 }
0103
0104 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
0105 #define MMSS_CC_CLK_NS_SRC__MASK                0x0000000f
0106 #define MMSS_CC_CLK_NS_SRC__SHIFT               0
0107 static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
0108 {
0109     return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
0110 }
0111 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK           0x00fff000
0112 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT          12
0113 static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
0114 {
0115     return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
0116 }
0117 #define MMSS_CC_CLK_NS_VAL__MASK                0xff000000
0118 #define MMSS_CC_CLK_NS_VAL__SHIFT               24
0119 static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
0120 {
0121     return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
0122 }
0123
0124 #define REG_MMSS_CC_DSI2_PIXEL_CC               0x00000094
0125
0126 #define REG_MMSS_CC_DSI2_PIXEL_NS               0x000000e4
0127
0128 #define REG_MMSS_CC_DSI2_PIXEL_CC2              0x00000264
0129
0130
0131 #endif /* MMSS_CC_XML */