msm/dsi/dsi_phy_28nm_8960.xml.h

0001 #ifndef DSI_PHY_28NM_8960_XML
0002 #define DSI_PHY_28NM_8960_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054
0055
0056 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
0057
0058 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
0059
0060 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
0061
0062 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
0063
0064 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
0065
0066 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
0067
0068 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
0069
0070 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0            0x00000100
0071
0072 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1            0x00000104
0073
0074 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2            0x00000108
0075
0076 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH        0x0000010c
0077
0078 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0            0x00000114
0079
0080 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1            0x00000118
0081
0082 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0         0x00000140
0083 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK      0x000000ff
0084 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT     0
0085 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
0086 {
0087     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
0088 }
0089
0090 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1         0x00000144
0091 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK     0x000000ff
0092 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT    0
0093 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
0094 {
0095     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
0096 }
0097
0098 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2         0x00000148
0099 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK   0x000000ff
0100 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT  0
0101 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
0102 {
0103     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
0104 }
0105
0106 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3         0x0000014c
0107
0108 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4         0x00000150
0109 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK       0x000000ff
0110 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT      0
0111 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
0112 {
0113     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
0114 }
0115
0116 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5         0x00000154
0117 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK       0x000000ff
0118 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT      0
0119 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
0120 {
0121     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
0122 }
0123
0124 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6         0x00000158
0125 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK    0x000000ff
0126 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT   0
0127 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
0128 {
0129     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
0130 }
0131
0132 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7         0x0000015c
0133 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK      0x000000ff
0134 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT     0
0135 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
0136 {
0137     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
0138 }
0139
0140 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8         0x00000160
0141 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK       0x000000ff
0142 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT      0
0143 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
0144 {
0145     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
0146 }
0147
0148 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9         0x00000164
0149 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK     0x00000007
0150 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT        0
0151 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
0152 {
0153     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
0154 }
0155 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK       0x00000070
0156 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT      4
0157 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
0158 {
0159     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
0160 }
0161
0162 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10            0x00000168
0163 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK       0x00000007
0164 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT      0
0165 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
0166 {
0167     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
0168 }
0169
0170 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11            0x0000016c
0171 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK    0x000000ff
0172 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT   0
0173 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
0174 {
0175     return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
0176 }
0177
0178 #define REG_DSI_28nm_8960_PHY_CTRL_0                0x00000170
0179
0180 #define REG_DSI_28nm_8960_PHY_CTRL_1                0x00000174
0181
0182 #define REG_DSI_28nm_8960_PHY_CTRL_2                0x00000178
0183
0184 #define REG_DSI_28nm_8960_PHY_CTRL_3                0x0000017c
0185
0186 #define REG_DSI_28nm_8960_PHY_STRENGTH_0            0x00000180
0187
0188 #define REG_DSI_28nm_8960_PHY_STRENGTH_1            0x00000184
0189
0190 #define REG_DSI_28nm_8960_PHY_STRENGTH_2            0x00000188
0191
0192 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0           0x0000018c
0193
0194 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1           0x00000190
0195
0196 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2           0x00000194
0197
0198 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3           0x00000198
0199
0200 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4           0x0000019c
0201
0202 #define REG_DSI_28nm_8960_PHY_LDO_CTRL              0x000001b0
0203
0204 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0     0x00000000
0205
0206 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1     0x00000004
0207
0208 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2     0x00000008
0209
0210 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3     0x0000000c
0211
0212 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4     0x00000010
0213
0214 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5     0x00000014
0215
0216 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG    0x00000018
0217
0218 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER       0x00000028
0219
0220 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0         0x0000002c
0221
0222 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1         0x00000030
0223
0224 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2         0x00000034
0225
0226 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0         0x00000038
0227
0228 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1         0x0000003c
0229
0230 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2         0x00000040
0231
0232 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3         0x00000044
0233
0234 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4         0x00000048
0235
0236 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS           0x00000050
0237 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY      0x00000010
0238
0239 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0            0x00000000
0240 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE         0x00000001
0241
0242 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1            0x00000004
0243
0244 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2            0x00000008
0245
0246 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3            0x0000000c
0247
0248 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4            0x00000010
0249
0250 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5            0x00000014
0251
0252 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6            0x00000018
0253
0254 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7            0x0000001c
0255
0256 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8            0x00000020
0257
0258 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9            0x00000024
0259
0260 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10           0x00000028
0261
0262 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11           0x0000002c
0263
0264 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12           0x00000030
0265
0266 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13           0x00000034
0267
0268 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14           0x00000038
0269
0270 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15           0x0000003c
0271
0272 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16           0x00000040
0273
0274 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17           0x00000044
0275
0276 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18           0x00000048
0277
0278 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19           0x0000004c
0279
0280 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20           0x00000050
0281
0282 #define REG_DSI_28nm_8960_PHY_PLL_RDY               0x00000080
0283 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY           0x00000001
0284
0285
0286 #endif /* DSI_PHY_28NM_8960_XML */