msm/dsi/dsi_phy_20nm.xml.h

0001 #ifndef DSI_PHY_20NM_XML
0002 #define DSI_PHY_20NM_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054
0055
0056 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
0057
0058 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
0059
0060 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
0061
0062 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
0063
0064 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
0065
0066 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
0067
0068 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
0069
0070 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
0071
0072 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
0073
0074 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
0075
0076 #define REG_DSI_20nm_PHY_LNCK_CFG_0             0x00000100
0077
0078 #define REG_DSI_20nm_PHY_LNCK_CFG_1             0x00000104
0079
0080 #define REG_DSI_20nm_PHY_LNCK_CFG_2             0x00000108
0081
0082 #define REG_DSI_20nm_PHY_LNCK_CFG_3             0x0000010c
0083
0084 #define REG_DSI_20nm_PHY_LNCK_CFG_4             0x00000110
0085
0086 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH         0x00000114
0087
0088 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL             0x00000118
0089
0090 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0             0x0000011c
0091
0092 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1             0x00000120
0093
0094 #define REG_DSI_20nm_PHY_TIMING_CTRL_0              0x00000140
0095 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK       0x000000ff
0096 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT      0
0097 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
0098 {
0099     return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
0100 }
0101
0102 #define REG_DSI_20nm_PHY_TIMING_CTRL_1              0x00000144
0103 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK      0x000000ff
0104 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT     0
0105 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
0106 {
0107     return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
0108 }
0109
0110 #define REG_DSI_20nm_PHY_TIMING_CTRL_2              0x00000148
0111 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK        0x000000ff
0112 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT       0
0113 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
0114 {
0115     return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
0116 }
0117
0118 #define REG_DSI_20nm_PHY_TIMING_CTRL_3              0x0000014c
0119 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8           0x00000001
0120
0121 #define REG_DSI_20nm_PHY_TIMING_CTRL_4              0x00000150
0122 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK        0x000000ff
0123 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT       0
0124 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
0125 {
0126     return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
0127 }
0128
0129 #define REG_DSI_20nm_PHY_TIMING_CTRL_5              0x00000154
0130 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK        0x000000ff
0131 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT       0
0132 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
0133 {
0134     return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
0135 }
0136
0137 #define REG_DSI_20nm_PHY_TIMING_CTRL_6              0x00000158
0138 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK     0x000000ff
0139 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT        0
0140 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
0141 {
0142     return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
0143 }
0144
0145 #define REG_DSI_20nm_PHY_TIMING_CTRL_7              0x0000015c
0146 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK       0x000000ff
0147 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT      0
0148 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
0149 {
0150     return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
0151 }
0152
0153 #define REG_DSI_20nm_PHY_TIMING_CTRL_8              0x00000160
0154 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK        0x000000ff
0155 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT       0
0156 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
0157 {
0158     return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
0159 }
0160
0161 #define REG_DSI_20nm_PHY_TIMING_CTRL_9              0x00000164
0162 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK          0x00000007
0163 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT         0
0164 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
0165 {
0166     return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
0167 }
0168 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK        0x00000070
0169 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT       4
0170 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
0171 {
0172     return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
0173 }
0174
0175 #define REG_DSI_20nm_PHY_TIMING_CTRL_10             0x00000168
0176 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK        0x00000007
0177 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT       0
0178 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
0179 {
0180     return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
0181 }
0182
0183 #define REG_DSI_20nm_PHY_TIMING_CTRL_11             0x0000016c
0184 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK     0x000000ff
0185 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT        0
0186 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
0187 {
0188     return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
0189 }
0190
0191 #define REG_DSI_20nm_PHY_CTRL_0                 0x00000170
0192
0193 #define REG_DSI_20nm_PHY_CTRL_1                 0x00000174
0194
0195 #define REG_DSI_20nm_PHY_CTRL_2                 0x00000178
0196
0197 #define REG_DSI_20nm_PHY_CTRL_3                 0x0000017c
0198
0199 #define REG_DSI_20nm_PHY_CTRL_4                 0x00000180
0200
0201 #define REG_DSI_20nm_PHY_STRENGTH_0             0x00000184
0202
0203 #define REG_DSI_20nm_PHY_STRENGTH_1             0x00000188
0204
0205 #define REG_DSI_20nm_PHY_BIST_CTRL_0                0x000001b4
0206
0207 #define REG_DSI_20nm_PHY_BIST_CTRL_1                0x000001b8
0208
0209 #define REG_DSI_20nm_PHY_BIST_CTRL_2                0x000001bc
0210
0211 #define REG_DSI_20nm_PHY_BIST_CTRL_3                0x000001c0
0212
0213 #define REG_DSI_20nm_PHY_BIST_CTRL_4                0x000001c4
0214
0215 #define REG_DSI_20nm_PHY_BIST_CTRL_5                0x000001c8
0216
0217 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL             0x000001d4
0218 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL       0x00000001
0219
0220 #define REG_DSI_20nm_PHY_LDO_CNTRL              0x000001dc
0221
0222 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0           0x00000000
0223
0224 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1           0x00000004
0225
0226 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2           0x00000008
0227
0228 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3           0x0000000c
0229
0230 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4           0x00000010
0231
0232 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5           0x00000014
0233
0234 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG          0x00000018
0235
0236
0237 #endif /* DSI_PHY_20NM_XML */