msm/dsi/dsi_phy_14nm.xml.h

0001 #ifndef DSI_PHY_14NM_XML
0002 #define DSI_PHY_14NM_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054
0055
0056 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0           0x00000000
0057
0058 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1           0x00000004
0059
0060 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2           0x00000008
0061
0062 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3           0x0000000c
0063
0064 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0               0x00000010
0065 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK        0x000000f0
0066 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT       4
0067 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
0068 {
0069     return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
0070 }
0071 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK        0x000000f0
0072 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT       4
0073 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
0074 {
0075     return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
0076 }
0077
0078 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1               0x00000014
0079 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL            0x00000001
0080
0081 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL         0x00000018
0082 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL       0x00000004
0083
0084 #define REG_DSI_14nm_PHY_CMN_CTRL_0             0x0000001c
0085
0086 #define REG_DSI_14nm_PHY_CMN_CTRL_1             0x00000020
0087
0088 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER             0x00000024
0089
0090 #define REG_DSI_14nm_PHY_CMN_SW_CFG0                0x00000028
0091
0092 #define REG_DSI_14nm_PHY_CMN_SW_CFG1                0x0000002c
0093
0094 #define REG_DSI_14nm_PHY_CMN_SW_CFG2                0x00000030
0095
0096 #define REG_DSI_14nm_PHY_CMN_HW_CFG0                0x00000034
0097
0098 #define REG_DSI_14nm_PHY_CMN_HW_CFG1                0x00000038
0099
0100 #define REG_DSI_14nm_PHY_CMN_HW_CFG2                0x0000003c
0101
0102 #define REG_DSI_14nm_PHY_CMN_HW_CFG3                0x00000040
0103
0104 #define REG_DSI_14nm_PHY_CMN_HW_CFG4                0x00000044
0105
0106 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL              0x00000048
0107 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START            0x00000001
0108
0109 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL              0x0000004c
0110 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK      0x0000003f
0111 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT     0
0112 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
0113 {
0114     return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
0115 }
0116
0117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
0118
0119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
0120 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK          0x000000c0
0121 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT         6
0122 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
0123 {
0124     return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
0125 }
0126
0127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
0128 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN         0x00000001
0129
0130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
0131
0132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
0133
0134 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
0135
0136 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
0137
0138 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
0139 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK     0x000000ff
0140 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT        0
0141 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
0142 {
0143     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
0144 }
0145
0146 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
0147 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK     0x000000ff
0148 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT        0
0149 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
0150 {
0151     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
0152 }
0153
0154 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
0155 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK      0x000000ff
0156 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT     0
0157 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
0158 {
0159     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
0160 }
0161
0162 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
0163 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK        0x000000ff
0164 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT       0
0165 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
0166 {
0167     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
0168 }
0169
0170 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
0171 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK     0x000000ff
0172 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT        0
0173 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
0174 {
0175     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
0176 }
0177
0178 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
0179 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK       0x00000007
0180 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT      0
0181 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
0182 {
0183     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
0184 }
0185 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK     0x00000070
0186 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT        4
0187 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
0188 {
0189     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
0190 }
0191
0192 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
0193 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK     0x00000007
0194 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT        0
0195 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
0196 {
0197     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
0198 }
0199
0200 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
0201 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK      0x000000ff
0202 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT     0
0203 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
0204 {
0205     return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
0206 }
0207
0208 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
0209
0210 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
0211
0212 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
0213
0214 #define REG_DSI_14nm_PHY_PLL_IE_TRIM                0x00000000
0215
0216 #define REG_DSI_14nm_PHY_PLL_IP_TRIM                0x00000004
0217
0218 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM             0x00000010
0219
0220 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN            0x0000001c
0221
0222 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET            0x00000028
0223
0224 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL          0x0000002c
0225
0226 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2         0x00000030
0227
0228 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3         0x00000034
0229
0230 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4         0x00000038
0231
0232 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5         0x0000003c
0233
0234 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1          0x00000040
0235
0236 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2          0x00000044
0237
0238 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1            0x00000048
0239
0240 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2            0x0000004c
0241
0242 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1              0x0000005c
0243
0244 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE              0x00000058
0245
0246 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1           0x0000006c
0247
0248 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2           0x00000070
0249
0250 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1             0x00000074
0251
0252 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2             0x00000078
0253
0254 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1           0x0000007c
0255
0256 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2           0x00000080
0257
0258 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3           0x00000084
0259
0260 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN         0x00000088
0261
0262 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE           0x0000008c
0263
0264 #define REG_DSI_14nm_PHY_PLL_DEC_START              0x00000090
0265
0266 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER          0x00000094
0267
0268 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1           0x00000098
0269
0270 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2           0x0000009c
0271
0272 #define REG_DSI_14nm_PHY_PLL_SSC_PER1               0x000000a0
0273
0274 #define REG_DSI_14nm_PHY_PLL_SSC_PER2               0x000000a4
0275
0276 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1         0x000000a8
0277
0278 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2         0x000000ac
0279
0280 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1            0x000000b4
0281
0282 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2            0x000000b8
0283
0284 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3            0x000000bc
0285
0286 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN               0x000000c0
0287
0288 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL             0x000000c4
0289
0290 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS      0x000000cc
0291
0292 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1              0x000000e8
0293
0294 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR             0x000000f0
0295
0296 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET            0x000000f4
0297
0298 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET            0x000000f8
0299
0300 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET            0x000000fc
0301
0302 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1               0x00000100
0303
0304 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV           0x00000104
0305
0306 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP            0x00000108
0307
0308
0309 #endif /* DSI_PHY_14NM_XML */