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0001 #ifndef DSI_PHY_10NM_XML
0002 #define DSI_PHY_10NM_XML
0003 
0004 /* Autogenerated file, DO NOT EDIT manually!
0005 
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009 
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029 
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033 
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041 
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045 
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054 
0055 
0056 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0           0x00000000
0057 
0058 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1           0x00000004
0059 
0060 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2           0x00000008
0061 
0062 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3           0x0000000c
0063 
0064 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0               0x00000010
0065 
0066 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1               0x00000014
0067 
0068 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL              0x00000018
0069 
0070 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL              0x0000001c
0071 
0072 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL              0x00000020
0073 
0074 #define REG_DSI_10nm_PHY_CMN_CTRL_0             0x00000024
0075 
0076 #define REG_DSI_10nm_PHY_CMN_CTRL_1             0x00000028
0077 
0078 #define REG_DSI_10nm_PHY_CMN_CTRL_2             0x0000002c
0079 
0080 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0              0x00000030
0081 
0082 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1              0x00000034
0083 
0084 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL              0x00000038
0085 
0086 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0             0x00000098
0087 
0088 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1             0x0000009c
0089 
0090 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2             0x000000a0
0091 
0092 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3             0x000000a4
0093 
0094 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4             0x000000a8
0095 
0096 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0          0x000000ac
0097 
0098 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1          0x000000b0
0099 
0100 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2          0x000000b4
0101 
0102 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3          0x000000b8
0103 
0104 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4          0x000000bc
0105 
0106 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5          0x000000c0
0107 
0108 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6          0x000000c4
0109 
0110 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7          0x000000c8
0111 
0112 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8          0x000000cc
0113 
0114 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9          0x000000d0
0115 
0116 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10         0x000000d4
0117 
0118 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11         0x000000d8
0119 
0120 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS             0x000000ec
0121 
0122 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0           0x000000f4
0123 
0124 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1           0x000000f8
0125 
0126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
0127 
0128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
0129 
0130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
0131 
0132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
0133 
0134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
0135 
0136 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
0137 
0138 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
0139 
0140 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
0141 
0142 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
0143 
0144 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
0145 
0146 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
0147 
0148 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
0149 
0150 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
0151 
0152 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE        0x00000000
0153 
0154 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO        0x00000004
0155 
0156 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE      0x00000010
0157 
0158 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER            0x0000001c
0159 
0160 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER           0x00000020
0161 
0162 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES           0x00000024
0163 
0164 #define REG_DSI_10nm_PHY_PLL_CMODE              0x0000002c
0165 
0166 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS       0x00000030
0167 
0168 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE    0x00000054
0169 
0170 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE       0x00000064
0171 
0172 #define REG_DSI_10nm_PHY_PLL_PFILT              0x0000007c
0173 
0174 #define REG_DSI_10nm_PHY_PLL_IFILT              0x00000080
0175 
0176 #define REG_DSI_10nm_PHY_PLL_OUTDIV             0x00000094
0177 
0178 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE          0x000000a4
0179 
0180 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE        0x000000a8
0181 
0182 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO     0x000000b4
0183 
0184 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1        0x000000cc
0185 
0186 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1       0x000000d0
0187 
0188 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1       0x000000d4
0189 
0190 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1      0x000000d8
0191 
0192 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1         0x0000010c
0193 
0194 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1        0x00000110
0195 
0196 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1          0x00000114
0197 
0198 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1         0x00000118
0199 
0200 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1       0x0000011c
0201 
0202 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1      0x00000120
0203 
0204 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL            0x0000013c
0205 
0206 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE            0x00000140
0207 
0208 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1         0x00000144
0209 
0210 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1       0x0000014c
0211 
0212 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1        0x00000154
0213 
0214 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1      0x0000015c
0215 
0216 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1   0x00000164
0217 
0218 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE          0x00000180
0219 
0220 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY         0x00000184
0221 
0222 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS            0x0000018c
0223 
0224 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE          0x000001a0
0225 
0226 
0227 #endif /* DSI_PHY_10NM_XML */
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