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0006 #ifndef _DP_LINK_H_
0007 #define _DP_LINK_H_
0008
0009 #include "dp_aux.h"
0010
0011 #define DS_PORT_STATUS_CHANGED 0x200
0012 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF
0013 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
0014
0015 struct dp_link_info {
0016 unsigned char revision;
0017 unsigned int rate;
0018 unsigned int num_lanes;
0019 unsigned long capabilities;
0020 };
0021
0022 enum dp_link_voltage_level {
0023 DP_TRAIN_VOLTAGE_SWING_LVL_0 = 0,
0024 DP_TRAIN_VOLTAGE_SWING_LVL_1 = 1,
0025 DP_TRAIN_VOLTAGE_SWING_LVL_2 = 2,
0026 DP_TRAIN_VOLTAGE_SWING_MAX = DP_TRAIN_VOLTAGE_SWING_LVL_2,
0027 };
0028
0029 enum dp_link_preemaphasis_level {
0030 DP_TRAIN_PRE_EMPHASIS_LVL_0 = 0,
0031 DP_TRAIN_PRE_EMPHASIS_LVL_1 = 1,
0032 DP_TRAIN_PRE_EMPHASIS_LVL_2 = 2,
0033 DP_TRAIN_PRE_EMPHASIS_MAX = DP_TRAIN_PRE_EMPHASIS_LVL_2,
0034 };
0035
0036 struct dp_link_test_video {
0037 u32 test_video_pattern;
0038 u32 test_bit_depth;
0039 u32 test_dyn_range;
0040 u32 test_h_total;
0041 u32 test_v_total;
0042 u32 test_h_start;
0043 u32 test_v_start;
0044 u32 test_hsync_pol;
0045 u32 test_hsync_width;
0046 u32 test_vsync_pol;
0047 u32 test_vsync_width;
0048 u32 test_h_width;
0049 u32 test_v_height;
0050 u32 test_rr_d;
0051 u32 test_rr_n;
0052 };
0053
0054 struct dp_link_test_audio {
0055 u32 test_audio_sampling_rate;
0056 u32 test_audio_channel_count;
0057 u32 test_audio_pattern_type;
0058 u32 test_audio_period_ch_1;
0059 u32 test_audio_period_ch_2;
0060 u32 test_audio_period_ch_3;
0061 u32 test_audio_period_ch_4;
0062 u32 test_audio_period_ch_5;
0063 u32 test_audio_period_ch_6;
0064 u32 test_audio_period_ch_7;
0065 u32 test_audio_period_ch_8;
0066 };
0067
0068 struct dp_link_phy_params {
0069 u32 phy_test_pattern_sel;
0070 u8 v_level;
0071 u8 p_level;
0072 };
0073
0074 struct dp_link {
0075 u32 sink_request;
0076 u32 test_response;
0077 bool psm_enabled;
0078
0079 u8 sink_count;
0080 struct dp_link_test_video test_video;
0081 struct dp_link_test_audio test_audio;
0082 struct dp_link_phy_params phy_params;
0083 struct dp_link_info link_params;
0084 };
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0093
0094 static inline u32 dp_link_bit_depth_to_bpp(u32 tbd)
0095 {
0096
0097
0098
0099
0100
0101
0102 switch (tbd) {
0103 case DP_TEST_BIT_DEPTH_6:
0104 return 18;
0105 case DP_TEST_BIT_DEPTH_8:
0106 return 24;
0107 case DP_TEST_BIT_DEPTH_10:
0108 return 30;
0109 case DP_TEST_BIT_DEPTH_UNKNOWN:
0110 default:
0111 return 0;
0112 }
0113 }
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123 static inline u32 dp_link_bit_depth_to_bpc(u32 tbd)
0124 {
0125 switch (tbd) {
0126 case DP_TEST_BIT_DEPTH_6:
0127 return 6;
0128 case DP_TEST_BIT_DEPTH_8:
0129 return 8;
0130 case DP_TEST_BIT_DEPTH_10:
0131 return 10;
0132 case DP_TEST_BIT_DEPTH_UNKNOWN:
0133 default:
0134 return 0;
0135 }
0136 }
0137
0138 void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link);
0139 u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp);
0140 int dp_link_process_request(struct dp_link *dp_link);
0141 int dp_link_get_colorimetry_config(struct dp_link *dp_link);
0142 int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status);
0143 bool dp_link_send_test_response(struct dp_link *dp_link);
0144 int dp_link_psm_config(struct dp_link *dp_link,
0145 struct dp_link_info *link_info, bool enable);
0146 bool dp_link_send_edid_checksum(struct dp_link *dp_link, u8 checksum);
0147
0148
0149
0150
0151
0152
0153
0154 struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux);
0155
0156 #endif